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AT17F32 데이터시트 PDF




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부품번호 AT17F32 기능
기능 FPGA Configuration Flash Memory
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로고 ATMEL Corporation 로고


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AT17F32 데이터시트, 핀배열, 회로
Features
Prowgwrwam.DmataaSbhleee3t43U,5.c5o4m,432 x 1-bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
3.3V Output Capability
5V Tolerant I/O Pins
Program Support using the Atmel ATDH2200E System or Industry Third Party
Programmers
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT40K and AT94K Devices, Altera® FLEX®, APEXDevices,
Stratix, Lattice Semiconductor® (ORCA®) FPGAs, Spartan®, VirtexFPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Low-power CMOS FLASH Process
Available in 44-lead PLCC Package
Emulation of Atmel’s AT24CXXX Serial EEPROMs
Low-power Standby Mode
Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System
Reconfiguration
Fast Serial Download Speeds up to 33 MHz
Endurance: 10,000 Write Cycles Typical
LHF Package Available (Lead and Halide Free)
FPGA
Configuration
Flash Memory
AT17F32
1. Description
The AT17F Series of In-System Programmable Configuration PROMs (Configurators)
provide an easy-to-use, cost-effective configuration memory for Field Programmable
Gate Arrays. The AT17F Series device is packaged in the 44-lead PLCC, see Table 1-
1. The AT17F Series Configurator uses a simple serial-access procedure to configure
one or more FPGA devices.
The AT17F Series Configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1-1. AT17F Series Packages
Package
44-lead PLCC
AT17F32
Yes
3393C–CNFG–6/05




AT17F32 pdf, 반도체, 판매, 대치품
5. Pin Description
www.DataSheet4U.com
Table 5-1. Pin Description
Name
DATA
CLK
PAGE_EN
PAGESEL0
PAGESEL1
RESET/OE
CE
GND
CEO
A2
READY
SER_EN
VCC
I/O
I/O
I
I
I
I
I
I
O
I
O
I
AT17F32
44
PLCC
2
5
1
20
25
19
21
24
27
29
41
44
5.1 DATA(1)
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
5.2 CLK(1)
Clock input. Used to increment the internal address and bit counter for reading and
programming.
5.3 PAGE_EN(2)
Input used to enable page download mode. When PAGE_EN is high the configuration download
address space is partitioned into 4 equal pages. This gives users the ability to easily store and
retrieve multiple configuration bitstreams from a single configuration device. This input works in
conjunction with the PAGESEL inputs. PAGE_EN must be remain Low if paging is not desired.
When SER_EN is Low (ISP mode) this pin has no effect.
Notes: 1. This pin has an internal 20 Kpull-up resistor.
2. This pin has an internal 30 Kpull-down resistor.
4 AT17F32
3393C–CNFG–6/05

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AT17F32 전자부품, 판매, 대치품
AT17F32
6. FPGA Master Serial Mode Summary
www.DataSheet4U.com The I/O and logic functions of any SRAM-based FPGA are established by a configuration pro-
gram. The program is loaded either automatically upon power-up, or on command, depending
on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the config-
uration program from an external memory. The AT17F Serial Configuration PROM has been
designed for compatibility with the Master Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xil-
inx applications.
7. Control of Configuration
Most connections between the FPGA device and the AT17F Serial Configurator PROM are sim-
ple and self-explanatory.
• The DATA output of the AT17F Series Configurator drives DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of the AT17F Series Configurator.
• The CEO output of any AT17F Series Configurator drives the CE input of the next
Configurator in a cascade chain of configurator devices.
• SER_EN must be at logic high level (internal pull-up provided) except during ISP.
• The READY pin is available as an open-collector indicator of the device’s reset status; it is
driven Low while the device is in its power-on reset cycle and released (tri-stated) when the
cycle is complete.
• PAGE_EN must be held Low if download paging is not desired. The PAGESEL[1:0] inputs
must be tied off High or Low. If paging is desired, PAGE_EN must be High and the PAGESEL
pins must be set to High or Low such that the desired page is selected, see Table 5-2 on
page 5.
8. Cascading Serial Configuration Devices
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration
memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator asserts its
CEO output Low and disables its DATA line driver. The second configurator recognizes the Low
level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if
the RESET/OE on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input can be
tied to its inactive (High) level.
9. Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be pro-
grammed by the 2-wire serial bus. The programming is done at VCC supply only. Programming
super voltages are generated inside the chip. The AT17F parts are read/write at 3.3V nominal.
Refer to the AT17F Programming Specification available on the Atmel web site
(www.atmel.com) for more programming details. AT17F devices are supported by the Atmel
ATDH2200 programming system along with many third party programmers.
3393C–CNFG–6/05
7

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