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AT25F512B 데이터시트 PDF




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부품번호 AT25F512B 기능
기능 512-Kilobit 2.7-volt Minimum SPI Serial Flash Memory
제조업체 ATMEL Corporation
로고 ATMEL Corporation 로고


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AT25F512B 데이터시트, 핀배열, 회로
Features
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Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
70 MHz Maximum Operating Frequency
– Clock-to-Output (tV) of 6 ns Maximum
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
– Uniform 4-Kbyte Block Erase
– Uniform 32-Kbyte Block Erase
– Full Chip Erase
Hardware Controlled Locking of Protected Sectors via WP Pin
128-Byte Programmable OTP Security Register
Flexible Programming
– Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
– 2.5 ms Typical Page Program (256 Bytes) Time
– 100 ms Typical 4-Kbyte Block Erase Time
– 500 ms Typical 32-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
– 6 mA Active Read Current (Typical at 20 MHz)
– 5 µA Deep Power-Down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (150-mil Wide)
– 8-pad Ultra Thin DFN (2 x 3 x 0.6 mm)
1. Description
The AT25F512B is a serial interface Flash memory device designed for use in a wide
variety of high-volume consumer based applications in which program code is shad-
owed from Flash memory into embedded or external RAM for execution. The flexible
erase architecture of the AT25F512B, with its erase granularity as small as 4 Kbytes,
makes it ideal for data storage as well, eliminating the need for additional data storage
EEPROM devices.
The erase block sizes of the AT25F512B have been optimized to meet the needs of
today's code and data storage applications. By optimizing the size of the erase blocks,
the memory space can be used much more efficiently. Because certain code modules
and data storage segments must reside by themselves in their own erase regions, the
wasted and unused memory space that occurs with large sectored and large block
erase Flash memory devices can be greatly reduced. This increased memory space
efficiency allows additional code routines and data storage segments to be added
while still maintaining the same overall device density.
The device also contains a specialized OTP (One-Time Programmable) Security Reg-
ister that can be used for purposes such as unique device serialization, system-level
Electronic Serial Number (ESN) storage, locked key storage, etc.
Specifically designed for use in 3-volt systems, the AT25F512B supports read, pro-
gram, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate
voltage is required for programming and erasing.
512-Kilobit
2.7-volt
Minimum
SPI Serial Flash
Memory
AT25F512B
Preliminary
3689C–DFLASH–12/08




AT25F512B pdf, 반도체, 판매, 대치품
4. Memory Array
www.DataSheet4U.com To provide the greatest flexibility, the memory array of the AT25F512B can be erased in three
levels of granularity including a full chip erase. The size of the erase blocks is optimized for both
code and data storage applications, allowing both code and data segments to reside in their own
erase regions. The Memory Architecture Diagram illustrates the breakdown of each erase level.
Figure 4-1. Memory Architecture Diagram
4 AT25F512B [Preliminary]
3689C–DFLASH–12/08

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AT25F512B 전자부품, 판매, 대치품
AT25F512B [Preliminary]
7. Read Commands
www.DataSheet4U.com
7.1 Read Array
The Read Array command can be used to sequentially read a continuous stream of data from
the device by simply providing the clock signal once the initial starting address has been speci-
fied. The device incorporates an internal address counter that automatically increments on every
clock cycle.
Two opcodes (0Bh and 03h) can be used for the Read Array command. The use of each
opcode depends on the maximum clock frequency that will be used to read data from the
device. The 0Bh opcode can be used at any clock frequency up to the maximum specified by
fCLK, and the 03h opcode can be used for lower frequency read operations up to the maximum
specified by fRDLF.
To perform the Read Array operation, the CS pin must first be asserted and the appropriate
opcode (0Bh or 03h) must be clocked into the device. After the opcode has been clocked in, the
three address bytes must be clocked in to specify the starting address location of the first byte to
read within the memory array. Following the three address bytes, an additional dummy byte
needs to be clocked into the device if the 0Bh opcode is used for the Read Array operation.
After the three address bytes (and the dummy byte if using opcode 0Bh) have been clocked in,
additional clock cycles will result in data being output on the SO pin. The data is always output
with the MSB of a byte first. When the last byte (00FFFFh) of the memory array has been read,
the device will continue reading back at the beginning of the array (000000h). No delays will be
incurred when wrapping around from the end of the array to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-
ance state. The CS pin can be deasserted at any time and does not require that a full byte of
data be read.
Figure 7-1. Read Array - 0Bh Opcode
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
OPCODE
ADDRESS BITS A23-A0
DON'T CARE
0 0 0 0 1 0 1 1AAAAAA
MSB
MSB
HIGH-IMPEDANCE
AAAXXXXXXXX
MSB
DATA BYTE 1
DDDDDDDDDD
MSB
MSB
Figure 7-2. Read Array - 03h Opcode
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36 37 38 39 40
OPCODE
ADDRESS BITS A23-A0
0 0 0 0 0 0 1 1AAAAAA
MSB
MSB
HIGH-IMPEDANCE
AAA
DATA BYTE 1
DDDDDDDDDD
MSB
MSB
3689C–DFLASH–12/08
7

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