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PDF AT49BV642DT Data sheet ( Hoja de datos )
| Número de pieza | AT49BV642DT | |
| Descripción | 64-megabit (4M x 16) 3-volt Only Flash Memory | |
| Fabricantes | ATMEL Corporation | |
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Features
• Sinwgwlew.VDoalttaaSgheeeOt4pUe.rcaotmion Read/Write: 2.65V - 3.6V
• 2.7V - 3.6V Read/Write
• Access Time – 70 ns
• Sector Erase Architecture
– One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout
– Eight 4K Word Sectors with Individual Write Lockout
• Fast Word Program Time – 10 µs
• Typical Sector Erase Time: 32K Word Sectors – 500 ms; 4K Word Sectors – 100 ms
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
• Low-power Operation
– 10 mA Active
– 15 µA Standby
• Data Polling and Toggle Bit for End of Program Detection
• VPP Pin for Write Protection and Accelerated Program Operations
• RESET Input for Device Initialization
• Sector Lockdown Support
• TSOP Package
• Top or Bottom Boot Block Configuration Available
• 128-bit Protection Register
• Common Flash Interface (CFI)
• Green (Pb/Halide-free) Packaging
64-megabit
(4M x 16)
3-volt Only
Flash Memory
AT49BV642D
AT49BV642DT
1. Description
The AT49BV642D(T) is a 2.7-volt 64-megabit Flash memory organized as 4,194,304
words of 16 bits each. The memory is divided into 135 sectors for erase operations.
The device can be read or reprogrammed off a single 2.7V power supply, making it
ideally suited for in-system programming.
To increase the flexibility of the device, it contains an Erase Suspend and Program
Suspend feature. This feature will put the erase or program on hold for any amount of
time and let the user read data from or program data to any of the remaining sectors.
The end of program or erase is detected by Data Polling or toggle bit.
The VPP pin provides data protection and faster programming times. When the VPP
input is below 0.4V, the program and erase functions are inhibited. When VPP is at
1.65V or above, normal program and erase operations can be performed. With VPP at
10.0V, the program (dual-word program command) operation is accelerated.
A six-word command (Enter Single Pulse Program Mode) to remove the requirement
of entering the three-word program sequence is offered to further improve program-
ming time. After entering the six-word code, only single pulses on the write control
lines are required for writing into the device. This mode (Single Pulse Word Program)
is exited by powering down the device, by taking the RESET pin to GND or by a high-
to-low transition on the VPP input. Erase, Erase Suspend/Resume, Program Sus-
pend/Resume and Read Reset commands will not work while in this mode; if entered
they will result in data being programmed into the device. It is not recommended that
the six-word code reside in the software of the final product but only exist in external
programming code.
3631A–FLASH–04/06
1 page  
AT49BV642D(T)
3.7.1 Data Polling
www.DataSheet4U.com
The AT49BV642D(T) features Data Polling to indicate the end of a program cycle. If the status
configuration register is set to a “00”, during a program cycle an attempted read of the last word
loaded will result in the complement of the loaded data on I/O7. Once the program cycle has
been completed, true data is valid on all outputs and the next cycle may begin. During a chip or
sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the program
or erase cycle has completed, true data will be read from the device. Data Polling may begin at
any time during the program cycle. Please see “Status Bit Table” on page 10 for more details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has completed
a program or erase operation. Once I/O7 has gone high, status information on the other pins can
be checked.
The Data Polling status bit must be used in conjunction with the erase/program and VPP status
bit as shown in the algorithm in Figures 3-1 and 3-2 on page 8.
3.7.2
Toggle Bit
In addition to Data Polling, the AT49BV642D(T) provides another method for determining the
end of a program or erase cycle. During a program or erase operation, successive attempts to
read data from the memory will result in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle. Please see “Status Bit Table” on page 10 for
more details.
The toggle bit status bit should be used in conjunction with the erase/program and VPP status bit
as shown in the algorithm in Figures 3-3 and 3-4 on page 9.
3.7.3
Erase/Program Status Bit
The device offers a status bit on I/O5 that indicates whether the program or erase operation has
exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable to
verify that an erase or a word program operation has been successfully performed. The device
may also output a “1” on I/O5 if the system tries to program a “1” to a location that was previ-
ously programmed to a “0”. Only an erase operation can change a “0” back to a “1”. If a program
(Sector Erase) command is issued to a protected sector, the protected sector will not be pro-
grammed (erased). The device will go to a status read mode and the I/O5 status bit will be set
high, indicating the program (erase) operation did not complete as requested. Once the
erase/program status bit has been set to a “1”, the system must write the Product ID Exit com-
mand to return to the read mode. The erase/program status bit is a “0” while the erase or
program operation is still in progress. Please see “Status Bit Table” on page 10 for more details.
3.7.4
VPP Status Bit
The AT49BV642D(T) provides a status bit on I/O3 that provides information regarding the volt-
age level of the VPP pin. During a program or erase operation, if the voltage on the VPP pin is
not high enough to perform the desired operation successfully, the I/O3 status bit will be a “1”.
Once the VPP status bit has been set to a “1”, the system must write the Product ID Exit com-
mand to return to the read mode. On the other hand, if the voltage level is high enough to
perform a program or erase operation successfully, the VPP status bit will output a “0”. Please
see “Status Bit Table” on page 10 for more details.
3631A–FLASH–04/06
5
5 Page 
AT49BV642D(T)
5. Command Definition Table
www.DataSheet4U.com
Command Sequence
Bus
Cycles
1st Bus
Cycle
Addr Data
2nd Bus
Cycle
Addr Data
3rd Bus
Cycle
Addr
Data
4th Bus
Cycle
Addr
Data
5th Bus
Cycle
Addr Data
6th Bus
Cycle
Addr Data
Read
Chip Erase
1
Addr
DOUT
6 555 AA AAA(2) 55
555
80
555
AA AAA 55 555 10
Sector Erase
6
555
AA
AAA
55
555
80
555
AA AAA 55 SA(3) 30
Word Program
4
555
AA
AAA
55
555
A0
Addr
DIN
Dual-Word Program(4)
5
555
AA
AAA
55
555
E0 Addr0
DIN0
Addr1 DIN1
Enter Single-pulse Program
Mode
6
555
AA
AAA
55
555
80
555
AA AAA 55 555 A0
Single-pulse Word Program
Mode
1
Addr
DIN
Sector Lockdown(5)
6
555
AA
AAA
55
555
80
555
AA
AAA
55 SA(3)(5) 60
Erase/Program Suspend
1 xxx B0
Erase/Program Resume
1 xxx 30
Product ID Entry(6)
3
555
AA
AAA
55
555
90
Product ID Exit(7)
3
555
AA
AAA
55
555 F0(8)
Product ID Exit(7)
1 xxx F0(8)
Program Protection
Register – Block B
4
555
AA
AAA
55
555
C0 Addr(9)
DIN
Lock Protection
Register – Block B
4
555
AA
AAA
55
555
C0
80
X0
Status of Block B
Protection
4
555
AA
AAA
55
555
90
80 DOUT(10)
Set Configuration Register
4
555
AA
AAA
55
555
D0
xxx 00/01(11)
CFI Query
1 X55 98
Notes:
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex). The ADDRESS FORMAT in
each bus cycle is as follows: A11 - A0 (Hex), A11 - A21 (Don’t Care).
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 13 - 16
for details).
4. The fast programming option enables the user to program two words in parallel only when VPP = 10V. The addresses, Addr0
and Addr1, of the two words, DIN0 and DIN1, must only differ in address A0. This command should be used for manufacturing
purpose only.
5. Once a sector is in the lockdown mode, the data in the protected sector cannot be changed, unless the chip is reset or power
cycled.
6. During the fourth bus cycle, the manufacturer code is read from address 00000H, the device code is read from address
00001H, and the data in the protection register is read from addresses 000081H - 000088H.
7. Either one of the Product ID Exit commands can be used.
8. Bytes of data other than F0 may be used to exit the product ID mode. However, it is recommended that F0 be used.
9. Any address within the user programmable register region. Please see “Protection Register Addressing Table” on page 12.
10. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
11. The default state (after power-up) of the configuration register is “00”.
3631A–FLASH–04/06
11
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| PDF Descargar | [ Datasheet AT49BV642DT.PDF ] | |
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