|
|
PDF AT80C31X2 Data sheet ( Hoja de datos )
| Número de pieza | AT80C31X2 | |
| Descripción | 8-bit CMOS Microcontroller ROMless | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AT80C31X2 (archivo pdf) en la parte inferior de esta página. Total 42 Páginas | ||
|
No Preview Available !
Features
• 80Cw3w1wC.DoamtaSphaetiebt4leU.com
• 8031 pin and instruction compatible
• Four 8-bit I/O ports
• Two 16-bit timer/counters
• 128 bytes scratchpad RAM
• High-Speed Architecture
• 40 MHz @ 5V, 30MHz @ 3V
• X2 Speed Improvement capability (6 clocks/machine cycle)
• 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to 60 MHz @ 5V, 40 MHz @ 3V)
• Dual Data Pointer
• Asynchronous port reset
• Interrupt Structure with
• 5 Interrupt sources,
• 4 priority level interrupt system
• Full duplex Enhanced UART
• Framing error detection
• Automatic address recognition
• Power Control modes
• Idle mode
• Power-down mode
• Power-off Flag
• Once mode (On-chip Emulation)
• Power supply: 4.5-5.5V, 2.7-5.5V
• Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC)
• Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1 (13.9 footprint)
8-bit CMOS
Microcontroller
ROMless
TS80C31X2
AT80C31X2
1. Description
TS80C31X2 is high performance CMOS and ROMless versions of the 80C51 CMOS
single chip 8-bit microcontroller.
The TS80C31X2 retains all features of the TSC80C31 with 128 bytes of internal RAM,
a 5-source, 4 priority level interrupt system, an on-chip oscilator and two
timer/counters.
In addition, the TS80C31X2 has a dual data pointer, a more versatile serial channel
that facilitates multiprocessor communication (EUART) and a X2 speed improvement
mechanism.
The fully static design of the TS80C31X2 allows to reduce system power consumption
by bringing the clock frequency down to any value, even DC, without loss of data.
The TS80C31X2 has 2 software-selectable modes of reduced activity for further
reduction in power consumption. In the idle mode the CPU is frozen while the timers,
the serial port and the interrupt system are still operating. In the power-down mode the
RAM is saved and all other functions are inoperative.
4428E–8051–02/08
1 page  
AT/TS80C31X2
www.DataSheet4U.com
Pin Number
Mnemonic
DIL LCC VQFP 1.4
VSS
Vss1
20 22
1
16
39
VCC
P0.0-P0.7
40 44
39-
32
43-36
38
37-30
P1.0-P1.7
P2.0-P2.7
1-8 2-9
40-44
1-3
21-
28
24-31
18-25
P3.0-P3.7
Reset
ALE
10-
17
11,
13-19
5,
7-13
10 11
11 13
12 14
13 15
14 16
15 17
16 18
17 19
9 10
30 33
5
7
8
9
10
11
12
13
4
27
PSEN
29 32
26
Type
I
I
I
I/O
I/O
I/O
I/O
I
O
I
I
I
I
O
O
I
O (I)
O
Name And Function
Ground: 0V reference
Optional Ground: Contact the Sales Office for ground connection.
Power Supply: This is the power supply voltage for normal, idle and power-down
operation
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written
to them float and can be used as high impedance inputs. Port 0 pins must be
polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0
is also the multiplexed low-order address and data bus during access to external
program and data memory. In this application, it uses strong internal pull-up when
emitting 1s.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 1 pins that are externally pulled low will source current
because of the internal pull-ups.
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 2 pins that are externally pulled low will source current
because of the internal pull-ups. Port 2 emits the high-order address byte during
fetches from external program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses
strong internal pull-ups emitting 1s. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 3 pins that are externally pulled low will source current
because of the internal pull-ups. Port 3 also serves the special features of the
80C51 family, as listed below.
RXD (P3.0): Serial input port
TXD (P3.1): Serial output port
INT0 (P3.2): External interrupt 0
INT1 (P3.3): External interrupt 1
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to VSS permits a power-on reset using
only an external capacitor to VCC.
Address Latch Enable: Output pulse for latching the low byte of the address during
an access to external memory. In normal operation, ALE is emitted at a constant
rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external
timing or clocking. Note that one ALE pulse is skipped during each access to
external data memory.
Program Store ENable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program
memory.
4428E–8051–02/08
5
5 Page 
AT/TS80C31X2
9. TS80C31X2 Serial I/O Port
www.DataSheet4U.com The serial I/O port in the TS80C31X2 is compatible with the serial I/O port in the 80C31.
It provides both synchronous and asynchronous communication modes. It operates as an Uni-
versal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2
and 3). Asynchronous transmission and reception can occur simultaneously and at different
baud rates
Serial I/O port includes the following enhancements:
• Framing error detection
• Automatic address recognition
9.1 Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To
enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 9-1).
Figure 9-1. Framing Error Block Diagram
SM0/FE SM1 SM2 REN TB8 RB8 TI
RI SCON (98h)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART mode control (SMOD = 0)
SMOD1 SMOD0 -
POF GF1 GF0 PD IDL PCON (87h)
To UART framing error control
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table
9-3.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only soft-
ware or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear
FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 9-
2. and Figure 9-3.).
Figure 9-2. UART Timings in Mode 1
RXD
D0 D1 D2 D3 D4 D5 D6 D7
RI
SMOD0=X
Start
bit
Data byte
Stop
bit
FE
SMOD0=1
4428E–8051–02/08
11
11 Page | ||
| Páginas | Total 42 Páginas | |
| PDF Descargar | [ Datasheet AT80C31X2.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AT80C31X2 | 8-bit CMOS Microcontroller ROMless | ATMEL Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |