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PDF AT69170E Data sheet ( Hoja de datos )
| Número de pieza | AT69170E | |
| Descripción | Space FPGA Configuration Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 4Mwbwitsw.xD1atNaSohneeVto4lUa.tciolemMemory Designed to Store Field Programmable Gate
Arrays (FPGAs) Configurations
• In-System Programming (ISP) via Two-Wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Atmel AT40KEL040 and ATF280E FPGAs
• Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
• Low-power RadHard non volatile CMOS process
• Programmable Reset Polarity
• Low-power Dissipation
– Active read: 18mW max
– Standby mode: 3.6mW max
• High-reliability
– Endurance: 50,000 Write Cycles (page mode)
– Data Retention: 10 Years
• 4Mbits On-chip Flash Array
– 512 bytes Page Write
• No Single Event Latch-up below a LET Threshold of 80MeV/mg/cm2
• Tested up to a Total Dose of 60KRads (Si) (according to MIL STD 883 Method 1019)
• Operating Range:
– Voltage: 3V to 3.6V
– Temperature: -55 to +125°C
• Quality Grades:
– QML-Q or V
– ESCC
• Package: 305 Mils FP18
• Mass: 10 grams
1. Description
The AT69170E FPGA configuration memory (configurator) is an electrically erasable
and re-programmable RadHard memory organized as 4Mx1bit. It is an easy-to-use
and cost-effective configuration memory for space Field Programmable Grid Array
(FPGA). It is manufactured with ATMEL 0.18µm low power non volatile CMOS
RadHard process.
It is packaged in a 18-pin 305 Mils wide Flat Pack package. AT69170E uses a simple
serial-access procedure to configure one or more FPGA devices. A two wire interface
(TWI) is available for memory programming.
The user can select the polarity of the reset function by programming a dedicated test
sequence. These devices also support a write-protection mechanism within its pro-
gramming mode.
The factory blanks devices to all ‘1’ before shipping.
Space FPGA
Configuration
Memory
AT69170E
Advanced
Information
7752A–AERO–07/07
1 page  
AT69170E
3.2.7 READY
www.DataSheet4U.com Open collector reset state indicator (output).
The READY line is driven Low during power-up reset. It is then released when power-up is com-
plete. It is recommended to use a 4.7 kΩ pull-up resistor when this pin is used.
3.2.8 PWD
Power Down input (active high)
Driving High the PWD input pin of the memory reduces the memory power consumption down to
less than 1mA. For normal operation of the memory, PWD pin shall be tied to a Low level.
3.2.9 VDD
Power supply input pin.
3.2.10 GND
Ground pin.
A 0.2 µF decoupling capacitor between VDD and GND is recommended.
7752A–AERO–07/07
5
5 Page 
Here is a summary of the process a programmer shall use to program one page in the memory.
www.DataSheet4U.com
Figure 7-3. Page Programming Summary - TWI Write
START
Send
Start Condition
Send
Device Address
R/W=0
Send MSB of
EEPROM Address
Send 2nd Byte of
Start Condition
Send LSB of
EEPROM Address
Yes
Yes
Yes
Send
Data Byte
No Yes
Last Byte ?
No
C_ACK?
C_ACK?
C_ACK?
C_ACK?
C_ACK?
No
No
No
No
Send
Stop Condition
END
7.2.1.1
C_ACK : Configurator send Acknowledge
Write polling
On receipt of the Stop Condition, the Configurator enters an internally-timed write cycle. While
the Configurator is busy with this write cycle, it will not acknowledge any transfers.
The programmer can start the next page write by sending the Start Condition followed by the
Device Address. As long as the internal write cycle is not ended, the AT69170E does not
acknowledge the Device byte. Then the programmer should abandon the transfer without
asserting a Stop Condition.
The programmer can then repeatedly initiate a write instruction as above, until an acknowledge
is received. When the Acknowledge Bit is received, the write instruction should continue by
sending the first EEPROM Address Byte to the Configurator.
12 AT69170E
7752A–AERO–07/07
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AT69170E.PDF ] | |
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