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AT73C237 데이터시트 PDF




ATMEL Corporation에서 제조한 전자 부품 AT73C237은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 AT73C237 기능
기능 Power Management and Analog Companions
제조업체 ATMEL Corporation
로고 ATMEL Corporation 로고


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AT73C237 데이터시트, 핀배열, 회로
Features
LDwOw1w: .2D.7at5aVSh(Deeet4faUu.clto)mand 1.8V (Programmable by TWI), 70 mA Linear Very Low Drop
Out Regulator with High PSRR and Low Noise.
LDO2: 1.8V (Default) and 1.5V (Programmable by TWI), 70 mA Linear Low Drop Out
Regulator with High PSRR and Low Noise.
LDO3: 1.8V (Default) and 1.5V or 1.2V (Programmable by TWI), 70 mA Linear Low Drop
Out Regulator with high PSRR and Low noise.
LDO4: 1.8V, 2mA Linear Low Drop Out Regulator with Very Low Quiescent Current, +/-
100 mV Adjustable.
Main Supply Rail from 2.8V to 5.5V
Independent Auxiliary Supply for LDO4 Backup Section, 2.8V to 5.5V
Internal State Machine for Startup and Delayed Reset Generation
Additional External Reset Input
Two Wire Interface for Independent Power Up/Power Down and Output Voltage
Programming for Each LDO.
LDOs Voltage Customization Possible on Request
Available in 3 x 3 x 0.9 mm 16-pin QFN Package
Applications: GPS Modules, WLAN Devices, Wireless Modules.
Power
Management
and Analog
Companions
(PMAAC)
1. Description
The AT73C237 is a four-channel Power Supply Power Management Unit (PMU) avail-
able in a small outline QFN 3 x 3mm package. It is a fully integrated, attractively
priced, combined Power Management device for wireless modules, GPS and WLAN
devices. It integrates 4X Linear Low Drop Out Regulators, three of which (LDO1, 2, 3)
provide high-accuracy RF performance and 1X (LDO4) with very low quiescent cur-
rent, that can be supplied by an external backup battery (VDD4) on a separate rail. An
internal Low Power Bandgap (LPBG) requiring no external capacitor for decoupling, is
used as reference voltage for LDO4 and starts when VDD4 is present. LDO4 regu-
lates its output voltage with extremely low quiescent current, maximizing the lifetime of
the backup battery.
An Internal State Machine manages the startup of the other LDOs. An economic High
Precision Bandgap (HPBG) provides highly accurate, low noise voltage reference to
LDOs 1, 2, 3 while operating in switching mode to optimize the quiescent current.
The AT73C237 features a Two-wire Interface (TWI) to increase the efficiency of the
system by disabling individually each LDO when not needed.
AT73C237
4-channel
Power
Management for
Wireless
Modules
6362A–PMAAC–01-Jul-08




AT73C237 pdf, 반도체, 판매, 대치품
4. Application Block Diagram
www.DataSheet4U.com
Figure 4-1. AT73C237 Application Block Diagram With GPS Module
J1 : "ON"
for 237
J2 : "OFF"
for 237
TWI
C5
C9
VBG (16) GNDA (15) VO1 (14)
XRESIN (1)
VDD1 (13)
TWD (12)
Core and IOs
C3
C7
VO3 (2)
VDD3 (3)
AT73C237
TWCK (11)
VO2 (10)
XRESO (4)
VO4 (5)
GNDD (6) VDD4 (7)
VDD2 (9)
VZAP (8)
C8
C4 D1 D2
C6
TX
C1
RX
C2
3V
Back up
Coin-Cell
Eg: Panasonic
CR1025
Li-Ion Battery
3.0V to 4.2V
Typical Application Components Design
Schematic Reference
Pin
C1 VO1
C2 VO2
C3 VO3
C4 VO4
C5 VDD1
C6 VDD2
C7 VDD3
C8 VDD4
C9
D1, D2
VBG
Description
2.2 µF ± 15% Ceramic Capacitor, X5R, 0402, 6.3V
MURATA®: GRM155R60J225ME15
TDK: C1005X5R0J225MT
1 µF ± 15% Ceramic Capacitor, X5R, 0402, 6.3V
MURATA: GRM155R60J105KE19
TDK: C1005X5R0J105KT
100 nF ± 15% Ceramic Capacitor, X5R, 0402, 10V
MURATA: GRM155R61A104KA01
TDK: C1005X5R1C104KT
ON-Semiconductor®: BAS70-04LT1
4 AT73C237
6362A–PMAAC–01-Jul-08

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AT73C237 전자부품, 판매, 대치품
AT73C237
6. Startup Procedure
www.DataSheet4U.com
6.1 At VDD4 Rising
• LPBG, LDO4, RCOSC start up
• POR connected to LDO4 output VO4 resets the state machine and enables:
– The reading of the internal fuses (TRIM cell in the application diagram) in order to
set up the programmed output voltage of LDO1, LDO2, LDO3, and the correct
reference voltage and oscillation frequency
– The Two Wire Interface
– Then under control of the state machine:
a. HPBG is turned on
b. After 4 ms, the Supply Monitor on VDD3 is turned on.
c. If VDD3 is present and greater than 2.7V, LDO1, 2, 3 are turned on. During LDO
regulator startup VDD3 voltage is checked.
d. Then XRESO is kept grounded for 180 ms, and set to “1” for 1ms before following
XRESIN. During that state VDD3 voltage is monitored and if lower than 2.6V, LDO
regulators 1, 2 and 3 are stopped and XRESO grounded.
Both XRESIN and the Supply Monitor on VDD3 are debounced at rising and falling edges for
two 10 kHz clock cycles. The debounce time is typically between 100 µs and 200 µs. Timings
are defined ± 40%.
6.2 At VDD3 Falling
• The Supply monitor generates a shut down control signal when VDD3 reaches 2.6V
• The State machine sets XRESO to logic “0”.
• The State machine switches off LDO1, LDO2, LDO3. HPBG is kept enabled in order to
assure a fast new startup of the LDOs.
6362A–PMAAC–01-Jul-08
7

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