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PDF ATSAM2195 Data sheet ( Hoja de datos )

Número de pieza ATSAM2195
Descripción Audio Processing
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo



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No Preview Available ! ATSAM2195 Hoja de datos, Descripción, Manual

Features
Sinwgwlew.CDhaitpaSAhelle-itn4U-o.cnoemDesign
– MIDI Control Processor, Serial and Parallel Interface
– Synthesis, General MIDI Wavetable Implementation
– General MIDI Compatible Effects: Reverb + Chorus
– Spatial Effect
– 4-band Stereo Equalizer
– Stereo DAC. DR: 86 dB min, THD+N: -80 dB max
State of the art Synthesis for Products Providing Best Quality for Price
– 64-voice Polyphony (without effects)
– 38-voice Polyphony + Effects
– On-chip CleanWaveWavetable Data, Firmware, RAM Delay Lines
Audio Stereo Line Output
Typical Applications: Battery Operated Musical Keyboards, Portable Phones, Karaokes
QFN44 (7mm x 7mm) Package: Small Footprint, Small Pin Count
Low Power
– 75 mW typ. Operating
– Single 3.3V or Single 1.8V Power Supply
– Built-in Power Switch and 3.3V to 1.8V Regulator
1. Typical Hardware Configuration
Figure 1-1. Typical Hardware Configuration
Audio
Processing
ATSAM2195
Low-power
Single Chip
Synthesizer
with Effects
MIDI In
Parallel MIDI
ATSAM2195
Audio
OUT
6308A–DRMSD–10-May-07

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ATSAM2195 pdf
2.2 Pinout By Pin Number - 44-lead QFN Package
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Table 2-6. Pinout
Pin# Pin Name
Pin# Pin Name
Pin#
1 AOUTL
12 CS
23
2 VA18
13 RD
24
3 VBG
14 WR
25
4 VA33
15 D0
26
5 AOUTR
16 D1
27
6 OUTLEV
17 D2
28
7 DITH0
18 D3
29
8 DITH1
19 VD18
30
9 RESET
20 GND
31
10 MIDI IN
21 VD33
32
11 A0
22 D4
33
Pin Name
D5
D6
D7
IRQ
TEST1
X2
X1
VD18
GND
TEST2
GND
ATSAM2195
Pin#
34
35
36
37
38
39
40
41
42
43
44
Pin Name
REGIN
OUTVC18
TEST0
PDWN
PWRIN
PWROUT
VCM
VREF
AGNDREF
AGND
AGND
6308A–DRMSD–10-May-07
5

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ATSAM2195 arduino
ATSAM2195
6. Timings
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6.1 Slave 8-bit Parallel Interface
This interface is typically used to connect the chip to an host processor.
Figure 6-1. 8-bit Parallel Interface Read Cycle
A0
CS
RD
D0 - D7
tAVCS
tCSLRDL
tPRD
tRDLDV
tRDHCSH
tDRH
IRQ
Figure 6-2. 8-bit Parallel Interface Write Cycle
A0
tAVCS
CS
tWRCYC
WR
tCSLWRL
tPWR
tWRHCSH
D0 - D7
tDWS tDWH
Table 6-1. Timings
Parameter
Address valid to chip select low
Chip select low to RD low
RD high to CS high
RD pulse width
Data out valid from RD
Data out hold from RD
6308A–DRMSD–10-May-07
Symbol
Min
Typ
Max Unit
tAVCS
tCSLRDL
tRDHCSH
tPRD
tRDLDV
tDRH
0
5
5
50
-
5
-
-
-
-
-
-
- ns
- ns
- ns
- ns
20 ns
10 ns
11

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