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29LV010 데이터시트 PDF




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기능 EN29LV010
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29LV010 데이터시트, 핀배열, 회로
www.DataSheet4U.com
E1dNMa20e9g.LaVbi0t1(0128K x 8-bit ) Uniform Sector,
CMOS 3.0 Volt-only Flash Memory
EN29LV010
FEATURES
Single power supply operation
- Full voltage range: 2.7-3.6 volt read and write
operations for battery-powered applications.
- Regulated voltage range: 3.0-3.6 volt read
and write operations for high performance
3.3 volt microprocessors.
High performance
- Full voltage range: access times as fast as 55
ns
- Regulated voltage range: access times as fast
as 45ns
Low power consumption (typical values at 5
MHz)
- 7 mA typical active read current
- 15 mA typical program/erase current
- 1 µA typical standby current (standard access
time to active mode)
Flexible Sector Architecture:
- Eight 16 Kbyte sectors
- Supports full chip erase
- Individual sector erase supported
- Sector protection and unprotection:
Hardware locking of sectors to prevent
program or erase operations within individual
sectors
High performance program/erase speed
- Byte program time: 8µs typical
- Sector erase time: 500ms typical
JEDEC Standard program and erase
commands
JEDEC standard DATA polling and toggle bits
feature
Single Sector and Chip Erase
Embedded Erase and Program Algorithms
Erase Suspend / Resume modes:
Read or program another Sector during
Erase Suspend Mode
triple-metal double-poly triple-well CMOS Flash
Technology
Low Vcc write inhibit < 2.5V
>100K program/erase endurance cycle
Package options
- 8mm x 20mm 32-pin TSOP (Type 1)
- 8mm x 14mm 32-pin TSOP (Type 1)
- 32-pin PLCC
-
Commercial and industrial Temperature Range
GENERAL DESCRIPTION
The EN29LV010 is a 1-Megabit, electrically erasable, read/write non-volatile flash memory,
organized as 131,072 bytes. Any byte can be programmed typically in 8µs. The EN29LV010
features 3.0V voltage read and write operation, with access times as fast as 45ns to eliminate the
need for WAIT states in high-performance microprocessor systems.
The EN29LV010 has separate Output Enable ( OE ), Chip Enable ( CE ), and Write Enable (WE)
controls, which eliminate bus contention issues. This device is designed to allow either single
Sector or full chip erase operation, where each Sector can be individually protected against
program/erase operations or temporarily unprotected to erase or program. The device can sustain a
minimum of 100K program/erase cycles on each Sector.
This Data Sheet may be revised by subsequent versions 1
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/01/05




29LV010 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
BLOCK DIAGRAM
EN29LV010
Vcc
Vss
WE#
State
Control
Command
Register
CE#
OE#
Vcc Detector
A0-A16
Block Protect Switches
Erase Voltage Generator
DQ0-DQ7
Input/Output Buffers
Program Voltage
Generator
Timer
Chip Enable
Output Enable
Logic
STB Data Latch
Y-Decoder
STB
X-Decoder
Y-Gating
Cell Matrix
This Data Sheet may be revised by subsequent versions
4
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/01/05

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29LV010 전자부품, 판매, 대치품
www.DataSheet4U.com
EN29LV010
whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. The system is not required to provide further controls or timings. The device automatically
provides internally generated program / erase pulses and verifies the programmed /erased cells’
margin. The host system can detect completion of a program or erase operation by reading the
DQ[7] (Data# Polling) and DQ[6] (Toggle) status bits.
The ‘Command Definitions’ section of this document provides details on the specific device
commands implemented in the EN29LV010.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The
hardware sector unprotection feature re-enables both program and erase operations in previously
protected sectors.
Sector protection/unprotection is intended only for programming equipment. This method requires
VID be applied to both OE# and A9 pin and non-standard microprocessor timings are used. This
method is described in a separate document called EN29LV010 Supplement, which can be obtained
by contacting a representative of Eon Silicon Solution, Inc.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enables this mode when addresses remain stable for tacc + 30ns. The automatic sleep mode is
independent of the CE#, WE# and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output is latched and always
available to the system. ICC4 in the DC Characteristics table represents the automatic sleep more
current specification.
This Data Sheet may be revised by subsequent versions
7
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/01/05

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