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PDF PLL520-06 Data sheet ( Hoja de datos )
| Número de pieza | PLL520-06 | |
| Descripción | (PLL520-0x) Low Phase Noise VCXO | |
| Fabricantes | PhaseLink Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PLL520-06 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
www.DataSheet4U.com
FEATURES
• 100MHz to 200MHz Fundamental Mode Crystal.
• Output range: 100 – 200MHz (no multiplication),
200 – 400MHz (2x multiplier), 400 – 800MHz (4x
multiplier), or 800MHz – 1GHz (PLL520-09
TSSOP only, 8x multiplier).
• High yield design supports up to 2pF stray
capacitance at 200MHz.
• CMOS (Standard drive PLL520-07 or Selectable
Drive PLL520-06), PECL (Enable low PLL520-08
or Enable high PLL520-05) or LVDS output
(PLL520-09).
• Integrated variable capacitors.
• Supports 3.3V-Power Supply.
• Available in 16-Pin (TSSOP or 3x3mm QFN)
Note: PLL520-06 only available in 3x3mm.
Note: PLL520-07 only available in TSSOP.
PIN CONFIGURATION
(Top View)
VDD
XIN
XOUT
SEL3^
SEL2^
OE
VCON
GND
1
2
3
4
5
6
7
8
16 SEL0^
15 SEL1^
14 GND
13 CLKC
12 VDD
11 CLKT
10 GND
9 GND
DESCRIPTION
The PLL520-05/-06/-07/-08/-09 is a family of VCXO
ICs specifically designed to pull high frequency
fundamental crystals. Their design was optimized to
tolerate higher limits of interelectrode capacitance
and bonding capacitance to improve yield. They
achieve very low current into the crystal resulting in
better overall stability. Their internal varicaps allow
an on chip frequency pulling, controlled by the
VCON input.
XIN
XOUT
SEL2^
OE
12 11 10 9
13 8
14 7
P520-0x
15 6
16 5
1234
GND
CLKC
VDD
CLKT
BLOCK DIAGRAM
SEL
VCON Oscillator
Amplifier
XIN
w/
integrated
varicaps
XOUT
PLL
(Phase
Locked
Loop)
PLL by-pass
^: Internal pull-up
*: PLL520-06 pin 12 is output drive select (DRIVSEL)
(0 for High Drive CMOS, 1 for Standard Drive CMOS)
OUTPUT ENABLE LOGICAL LEVELS
OE
Part #
OE
State
Q
Q
PLL520-08
PLL520-05
0 (Default)
1
0
Output enabled
Tri-state
Tri-state
PLL520-06
PLL520-07 1 (Default) Output enabled
PLL520-09
OE input: Logical states defined by PECL levels for PLL520-08
Logical states defined by CMOS levels for PLL520-05/-06/-
07/-09
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1
1 page  
PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
www.DataSheet4U.com
8. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
VDD Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
SYMBOL
VOD
∆VOD
VOH
VOL
VOS
∆VOS
IOXD
IOSD
CONDITIONS
RL = 100 Ω
(see figure)
Vout = VDD or GND
VDD = 0V
MIN.
247
-50
0.9
1.125
0
TYP.
355
1.4
1.1
1.2
3
±1
-5.7
MAX.
454
50
1.6
1.375
25
±10
-8
UNITS
mV
mV
V
V
V
mV
uA
mA
9. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
SYMBOL
tr
tf
CONDITIONS
RL = 100 Ω
CL = 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Levels Test Circuit
OUT
OUT
VOD
50Ω
VOS
50Ω
LVDS Switching Test Circuit
OUT
CL = 10pF
VDIFF
OUT
CL = 10pF
RL = 100Ω
LVDS Transistion Time Waveform
OUT
OUT
0V (Differential)
VDIFF
0V
20%
80%
tR
80%
20%
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet PLL520-06.PDF ] | |
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