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PDF PLL520-17 Data sheet ( Hoja de datos )
| Número de pieza | PLL520-17 | |
| Descripción | (PLL520-1x) Low Phase Noise VCXO | |
| Fabricantes | PhaseLink Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PLL520-17 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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PLL520-17/-18/-19
www.LDaotaSwheePt4Uh.caomse Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
FEATURES
• 65MHz to 130MHz Fundamental Mode Crystal.
• Output range: 65MHz – 800MHz (selectable 1x,
2x, 4x and 8x multipliers).
• Low Injection Power for crystal 50uW.
• Available outputs: PECL, LVDS, or CMOS.
• Integrated variable capacitors.
• Supports 3.3V-Power Supply.
• Available in 16 pin (TSSOP or SOIC)
DESCRIPTION
The PLL520-17/-18/-19 family of VCXO IC’s is
specifically designed to pull high frequency
fundamental crystals. They achieve very low current
into the crystal resulting in better overall stability.
Their internal varicaps allow an on chip frequency
pulling, controlled by the VCON input.
BLOCK DIAGRAM
PIN CONFIGURATION
VDD
XIN
XOUT
SEL3^
SEL2^
OE
VCON
GND
1
2
3
4
5
6
7
8
16 SEL0^
15 SEL1^
14 GND
13 CLKC
12 VDD
11 CLKT
10 GND
9 GND
^: Internal pull-up
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL520-18
PLL520-17
PLL520-19
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
OE input: Logical states defined by PECL levels for PLL520-18
Logical states defined by CMOS levels for PLL520-17/-19
SEL
VCON
XIN
XOUT
Oscillator
Amplifier
w/
integrated
varicaps
PLL
(Phase
Locked
Loop)
OE
Q
Q
PLL by-pass
PLL520-17/-18/-19
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1
1 page  
PLL520-17/-18/-19
www.LDaotaSwheePt4Uh.caomse Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
8. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
VDD Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
SYMBOL
VOD
∆VOD
VOH
VOL
VOS
∆VOS
IOXD
IOSD
CONDITIONS
RL = 100 Ω
(see figure)
Vout = VDD or GND
VDD = 0V
MIN.
247
-50
0.9
1.125
0
TYP.
355
1.4
1.1
1.2
3
±1
-5.7
MAX.
454
50
1.6
1.375
25
±10
-8
UNITS
mV
mV
V
V
V
mV
uA
mA
9. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
SYMBOL
tr
tf
CONDITIONS
RL = 100 Ω
CL = 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Levels Test Circuit
OUT
OUT
VOD
50Ω
VOS
50Ω
LVDS Switching Test Circuit
OUT
CL = 10pF
VDIFF
OUT
CL = 10pF
RL = 100Ω
LVDS Transistion Time Waveform
OUT
OUT
0V (Differential)
VDIFF
0V
20%
80%
tR
80%
20%
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PLL520-17.PDF ] | |
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