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PDF ARA2017 Data sheet ( Hoja de datos )
| Número de pieza | ARA2017 | |
| Descripción | Programmable Gain Amplifier | |
| Fabricantes | Anadigics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ARA2017 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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features
• High Linearity, High Output Power Integrated
Amplifier with Programmable Gain Control
• Attenuation Range: 0-58 dB, Adjustable in
2 dB Increments via a 3-wire Serial Control
• 33 dB Gain (at Minimum Attenuation)
• Low Distortion Products at Output Power Levels
up to +64 dBmV
• Low Noise Figure and Output Noise
• Frequency range: 5-85 MHz
• 5 V Operation
• Materials set consistent with RoHS Directors.
Surface Mount Package
Applications
• DOCSIS 3.0 Data Cable Modems and E-MTAs
• CATV Set Top Boxes
PRODUCT DESCRIPTION
The ARA2017 is a highly linear, high output power,
programmable gain amplifier optimized for DOCSIS
3.0 cable modem and E-MTA applications. Using a
low noise input amplification stage and an ultra linear
output driver amplifier, the device generates extremely
low distortion products at the high output power levels
required by DOCSIS 3.0 signals. Its balanced circuit
design provides superior harmonic performance
and an integrated digitally-controlled, multiple-stage
precision step attenuator enables system solutions to
meet DOCSIS power step accuracy requirements.
ARA2017
Programmable Gain Amplifier
PRELIMINARY DATA SHEET - rev 1.0
S29 Package
28-Pin QFN
5 mm x 5 mm x 1 mm
The ARA2017 supports output power levels of +64
dBmV while minimizing harmonic, distortion, and
output noise levels. Its precision attenuator provides
up to 58 dB of attenuation in 2 dB increments. The
attenuator setting is programmed via a 3-wire serial
interface, as is the output stage current, a feature
which allows the device to be operated in reduced
power modes for extended backup battery life in
E-MTA applications. The ARA2017 is offered in a 28-
pin 5 mm x 5 mm x 1 mm QFN package.
Figure 1: Functional Block Diagram
07/2008
1 page  
DATA PLOTS
figure ?: Gain vs frequency over Voltage
( Tc = 25oc )
Figure 3: Gain vs Frequency over Voltage
(TC = 25 8C)
w36ww.DataSheet4VUD.Dco=m
+5V
+5.25V
+5.5V
+4.75V
+4.5V
35.5
35
34.5
34
33.5
33
0
20 40 60 80 100
frequency (Mhz)
ARA2017
120
figure ?: Gain vs Temperature
F( iVgDucre=4:+G5Va,infv1s=T1e0mMpHezra)ture
(VDC = +5V, F1 = 10 MHz)
Gain dB
NF dB
36
7
35 6
34 5
33 4
32 3
31 2
30
0
1
20 40 60 80 100 120
Temperature(case)oc
PRELIMINARY DATA SHEET - Rev 1.0
07/2008
5
5 Page 
LOGIC PROGRAMMING
ARA2017
Programming Instructions
The programming word is set through a 10 bit shift
regiswtewrwv.iDaattahSehedeatt4aU,.ccolomck and enable lines. The
data is entered in order with the most significant bit
(MSB) first and the least significant bit (LSB) last. The
enable line must be low for the duration of the data
entry, then set high to latch the shift register. The
rising edge of the clock pulse shifts each data value
into the register.
Table 6: Programming Register
DATA BIT
9
8
7
6
5
4
3
2
10
fuNcTIoN
Current
Gain
Notes:
1. Refer to Application Information section for Current and Gain bit settings.
2. Data bit 0 should always be set to “1”.
3. Data bit 1 is reserved for future use, and should be set to “0”.
01
Figure 14: Serial Data Input Timing
PRELIMINARY DATA SHEET - Rev 1.0
07/2008
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ARA2017.PDF ] | |
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