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PDF MX23J12840 Data sheet ( Hoja de datos )
| Número de pieza | MX23J12840 | |
| Descripción | 128M-BIT NAND INTERFACE XtraROMTM | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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MX23J12840
128M-BIT NAND INTERFACE XtraROMTM
FEATURES
• Word organization
- (16,777,216 + 1,048,576Note) by 8 bits
• Page size
- (512 + 16Note) by 8 bits
• Block size
- (16,384 + 512Note) by 8 bits
Note : Underlined parts are redundancy and fixed to
all FFH.
• Operation mode
- READ mode (1), READ mode (2), READ mode (3),
RESET
• Operating supply voltage : VCC = 2.7~3.6V
• Access Time
- Memory cell array to starting address : 7 us (MAX.)
- Read cycle time : 50 ns (MAX.)
- RE access time : 35 ns (MAX.)
• Operating supply current
- During read : 30 mA (MAX.) (50 ns cycle operation)
- During standby (CMOS) : 40 uA (MAX.)
• Package Type
- 48-pin TSOP(I) (12mmx20mm)
• XtraROMTM : factory pre-programmed ROM with
Macronix NBitTM technology, supporting short TAT
• Process
- 0.15um
PIN CONFIGURATIONS
48 TSOP
NC 1
NC 2
NC 3
NC 4
NC 5
GND 6
RB 7
RE 8
CE 9
NC 10
NC 11
VCC 12
VSS 13
NC 14
NC 15
CLE 16
ALE 17
WE 18
NC 19
NC 20
NC 21
NC 22
NC 23
NC 24
MX23J12840
(Normal Type)
48 NC
47 NC
46 NC
45 NC
44 I/O7
43 I/O6
42 I/O5
41 I/O4
40 NC
39 NC
38 NC
37 VCC
36 GND
35 NC
34 NC
33 NC
32 I/O3
31 I/O2
30 I/O1
29 I/O0
28 NC
27 NC
26 NC
25 NC
PIN DESCRIPTION
SYMBOL
I/O0~I/O7
CLE
ALE
WE
RE
CE
RB
VCC
NC
GND
PIN NAME
Address Input/Command Inputs/
Data Outputs
Command Latch Enable
Address Latch Enable
Write Enable
Read Enable
Chip Enable
READY, /BUSY pin
Supply Voltage
No Connection
Ground
ORDER INFORMATION
Part No.
MX23J12840TC-50G
MX23J12840TC-50
MX23J12840TI-50G
P/N:PM1097
Package
48 pin TSOP (Pb-free, RoHS)
48 pin TSOP
48 pin TSOP (Pb-free, RoHS)
1
Grade
Commercial
Commercial
Industrial
REV. 1.2, OCT. 28, 2005
1 page  
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Operation Commands
MX23J12840
The following six operation settings are possible by inputting commands from I/O pins.
Command
Read mode(1)
Read mode(2)
Read mode(3)Note1
Reset Note2
Hex I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Command receivable
during Busy
00 L L L L L L L L
01 L L L L L L L H
50 L H L H L L L L
FF H H H H H H H H
Notes:
1. The data output in read mode (3) is all FFH.
2.The only command that can be executed when the device is Busy is the reset command. Do not set any of the other
commands while the device is Busy.
I/O Pin Correspondence Table during Address Input Cycle (Address Setting)
(1) When 00H or 01H command is set [Read mode (1), Read mode (2)]
Command
I/O7 I/O6 I/O5 I/O4
I/O3 I/O2 I/O1
1st address cycle
A7 A6 A5 A4
A3 A2 A1
2nd address cycle
A16 A15 A14 A13
A12 A11 A10
3rd address cycle
X
A23 A22 A21
A20 A19 A18
I/O0
A0
A9
A17
(2) When 50H command is set [Read mode (3)]
Command
I/O7 I/O6
1st address cycle
XX
2nd address cycle
A16 A15
3rd address cycle
X A23
I/O5 I/O4
XX
A14 A13
A22 A21
I/O3 I/O2 I/O1
A3 A2 A1
A12 A11 A10
A20 A19 A18
I/O0
A0
A9
A17
Remarks
1. A0 to A23 are internal addresses.
2. Internal address A8 is set internally with command 00H or 01H.
3. When 50H command is set [read mode (3)], the I/O4, I/O5, I/O6, and I/O7 inputs of the 1st address cycle are VIH
or VIL.
P/N:PM1097
REV. 1.2, OCT. 28, 2005
5
5 Page 
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READ CYCLE TIMING CHART (3)
(In case of read mode (3))
CLE
tCLS tCLH
MX23J12840
CE
tCS
tWC
WE
tALH tALS tWP tWH
ALE
tR
tALH tAR2
tCEH
tCRY
tCHZ
RE
tDS tDH
I/O0~
I/O7
50H
RB
tWB
tDS tDS tDS tDS
A0-A3 A9-A16 A17-A24 A25
tDH tDH tDH tDH
tRR tRC
tRC
tRP tREH
tRHZ
DOUT DOUT
512+N 512+N+1
tREA
tRHZ
DOUT
527
tRB
Access
page M
Output Page M Data
Remarks
1. Start address (SA) specification when read is performed with command 50H. N: 0 to 15
2. The start address of area C (redundancy data) is specified with A0 tp A3 during the 1st address cycle. At this time,
A4 to A7 are Don't Care.
3. The time (tCRY) from CE high level until Busy is cancelled depends on the pull-up register of the RB output pin.
P/N:PM1097
REV. 1.2, OCT. 28, 2005
11
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