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ATXMEGA192A3 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 ATXMEGA192A3
기능 (ATXMEGAxxxA3) 8/16-bit XMEGA A3 Microcontroller
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ATXMEGA192A3 데이터시트, 핀배열, 회로
Features
Higwhw-pwe.DrfaotarSmhaenect4eU,.Lcoomw-power AVR 8/16-bit XMEGA Microcontroller
Non-volatile Program and Data Memories
– 64K - 256K Bytes of In-System Self-Programmable Flash
– 4K - 8K Boot Code Section with Independent Lock Bits
– 2K - 4K Bytes EEPROM
– 4K - 16K Bytes Internal SRAM
Peripheral Features
– Four-channel DMA Controller with support for external requests
– Eight-channel Event System
– Seven 16-bit Timer/Counters
Four Timer/Counters with 4 Output Compare or Input Capture channels
Three Timer/Counters with 2 Output Compare or Input Capture channels
High Resolution Extensions on all Timer/Counters
Advanced Waveform Extension on one Timer/Counter
– Seven USARTs
IrDA Extension on 1 USART
– AES and DES Crypto Engine
– Two Two-wire Interfaces with dual address match(I2C and SMBus compatible)
– Three SPI (Serial Peripheral Interfaces)
– 16-bit Real Time Counter with Separate Oscillator
– Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters
– One Two-channel, 12-bit, 1 Msps Digital to Analog Converter
– Four Analog Comparators with Window compare function
– External Interrupts on all General Purpose I/O pins
– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal and External Clock Options with PLL
– Programmable Multi-level Interrupt Controller
– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby
– Advanced Programming, Test and Debugging Interfaces
JTAG (IEEE 1149.1 Compliant) Interface for test, debug and programming
PDI (Program and Debug Interface) for programming, test and debugging
I/O and Packages
– 50 Programmable I/O Lines
– 64-lead TQFP
– 64-pad MLF
Operating Voltage
– 1.6 – 3.6V
Speed performance
– 0 – 12 MHz @ 1.6 – 3.6V
– 0 – 32 MHz @ 2.7 – 3.6V
Typical Applications
Industrial control
Factory automation
Building control
Board control
White Goods
Climate control
ZigBee
Motor control
Networking
Optical
Hand-held battery applications
Power tools
HVAC
Metering
Medical Applications
8/16-bit
XMEGA A3
Microcontroller
ATxmega256A3
ATxmega192A3
ATxmega128A3
ATxmega64A3
Preliminary
8068E–AVR–08/08




ATXMEGA192A3 pdf, 반도체, 판매, 대치품
3.1 Block Diagram
www.DataSheet4U.com
Figure 3-1. XMEGA A3 Block Diagram
PR[0..1]
XTAL1
XTAL2
XMEGA A3
PA[0..7]
PB[0..7]/
JTAG
PORT A (8)
ACA
ADCA
AREFA
Internal
Reference
AREFB
ADCB
ACB
PORT B (8)
DACB
IRCOM
Event System
Controller
DMA
Controller
BUS
Controller
DES
AES
Oscillator
Circuits/
Clock
Generation
DATA BUS
Real Time
Counter
Watchdog
Oscillator
Watchdog
Timer
SRAM
Oscillator
Control
Sleep
Controller
Prog/Debug
Controller
Power
Supervision
POR/BOD &
RESET
PDI
JTAG
PORT B
CPU
OCD
Interrupt
Controller
NVM Controller
Flash
EEPROM
USARTF0
TCF0
DATA BUS
EVENT ROUTING NETWORK
VCC
GND
RESET/
PDI_CLK
PDI_DATA
PF[0..7]
8068E–AVR–08/08
PORT C (8)
PC[0..7]
PORT D (8)
PD[0..7]
PORT E (8)
To Clock
Generator
TOSC1
TOSC2
PE[0..7]
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ATXMEGA192A3 전자부품, 판매, 대치품
XMEGA A3
This concept enables instructions to be executed in every clock cycle. The program memory is
www.DataSheet4U.com In-System Re-programmable Flash memory.
6.3 Register File
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File - in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing - enabling efficient address calculations. One of these address pointers can
also be used as an address pointer for look up tables in Flash program memory.
6.4 ALU - Arithmetic Logic Unit
The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations
between registers or between a constant and a register. Single register operations can also be
executed. Within a single clock cycle, arithmetic operations between general purpose registers
or between a register and an immediate are executed. After an arithmetic or logic operation, the
Status Register is updated to reflect information about the result of the operation.
The ALU operations are divided into three main categories – arithmetic, logical, and bit-func-
tions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for easy
implementation of 32-bit arithmetic. The ALU also provides a powerful multiplier supporting both
signed and unsigned multiplication and fractional format.
6.5 Program Flow
When the device is powered on, the CPU starts to execute instructions from the lowest address
in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to
be fetched. After a reset, the PC is set to location ‘0’.
Program flow is provided by conditional and unconditional jump and call instructions, capable of
addressing the whole address space directly. Most AVR instructions use a 16-bit word format,
while a limited number uses a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited
by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to
the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory
space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can
easily be accessed through the five different addressing modes supported in the AVR CPU.
8068E–AVR–08/08
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