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K7J641882M 데이터시트 PDF




Samsung semiconductor에서 제조한 전자 부품 K7J641882M은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 K7J641882M 기능
기능 (K7J641882M / K7J643682M) 72Mb M-die DDRII SRAM Specification
제조업체 Samsung semiconductor
로고 Samsung semiconductor 로고


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K7J641882M 데이터시트, 핀배열, 회로
K7J643682M
wKww7.DJata6S4he1et84U8.c2omM
2Mx36 & 4Mx18 DDR II SIO b2 SRAM
72Mb M-die DDRII SRAM Specification
165 FBGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure couldresult in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 - Aug. 2005
Rev 1.0




K7J641882M pdf, 반도체, 판매, 대치품
K7J643682M
wKww7.DJata6S4he1et84U8.c2omM
2Mx36 & 4Mx18 DDR II SIO b2 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7J643682M(2Mx36)
1 2 3 4 5 6 7 8 9 10 11
A
CQ VSS/SA* SA
R/W
BW2
K
BW1
LD
SA VSS/SA* CQ
B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8
C D27 Q28 D19 VSS
SA
SA
SA VSS D16 Q7
D8
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS VDDQ Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS VDDQ D11
Q11
Q2
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1
D2
N D34 D26 Q25 VSS
SA
SA
SA VSS Q10 D9
D1
P Q35 D35 Q26
SA
SA
C
SA SA Q9 D0 Q0
R TDO TCK
SA
SA
SA
C
SA SA SA TMS TDI
Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 144Mb and 2A for 288Mb.
2. BW0 controls write to D0:D8, BW1 controls write to D9:D17, BW2 controls write to D18:D26 and BW3 controls write to D27:D35.
PIN NAME
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA
D0-35
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
3A,9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L
9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N
1C,1D,2E,1G,1J,2K,1M,1N,2P
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Address Inputs
Data Inputs
NOTE
1
Q0-35
R/W
11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L
9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N
3P,1B,2C,1E,1F,2J,1K,1L,2M,1P
4A
LD 8A
BW0, BW1,BW2, BW3
VREF
ZQ
VDD
VDDQ
VSS
TMS
TDI
TCK
TDO
NC
7B,7A,5A,5B
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M,
8M,4N,8N
10R
11R
2R
1R
-
Data Outputs
Read, Write Control Pin, Read active
when high
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
Block Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
Output Power Supply ( 1.5V or 1.8V )
Ground
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
No Connect
2
3
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
- 4 - Aug. 2005
Rev 1.0

4페이지










K7J641882M 전자부품, 판매, 대치품
K7J643682M
wKww7.DJata6S4he1et84U8.c2omM
2Mx36 & 4Mx18 DDR II SIO b2 SRAM
Single Clock Mode
K7J643682M and K7J641882M can be operated with the single clock pair K and K, insted of C or C for output clocks.
To operate these devices in single clock mode, C and C must be tied high during power up
and must be maintained high during operation.
After power up, this device cant change to or from single clock mode.
System flight time and clock skew could not be compensated in this mode.
Depth Expansion
Separate input and output ports enables easy depth expansion.
Each port can be selected and deselected independently and read and write operation do not affect each other.
Before chip deselected, all read and write pending operations are completed.
Programmable Impedance Output Buffer Operation
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250resistor will give an output impedance of 50.
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous
behavior in the SRAM.
There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the
SRAM needs 1024 non-read cycles.
Echo clock operation
To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures as output driver.
Clock Consideration
K7J643682M and K7J641882M utlizes internal DLL(Delay-Locked Loops) for maximum output data valid window.
It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.
Circuitry automatically resets the DLL when absence of input clock is detected.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
- 7 - Aug. 2005
Rev 1.0

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K7J641882M

(K7J641882M / K7J643682M) 72Mb M-die DDRII SRAM Specification

Samsung semiconductor
Samsung semiconductor

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