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CH7011A 데이터시트 PDF




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부품번호 CH7011A 기능
기능 Chrontel CH7011 TV Output Device
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CH7011A 데이터시트, 핀배열, 회로
CH7011A
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www.DataSheet4U.com
Chrontel CH7011 TV Output Device
1. FEATURES
2. GENERAL DESCRIPTION
• TV output supporting graphics resolutions up to
1024x768 pixels
• Macrovision7.1.L1 copy protection support
• Programmable digital interface supports RGB and
YCrCb
• True scale rendering engine supports underscan in all
TV output resolutions
• Enhanced text sharpness and adaptive flicker
removal with up to 7 lines of filtering
• Support for all NTSC and PAL formats
• Provides CVBS, S-Video and SCART (RGB) outputs
• TV Programmable power management
• 10-bit video DAC outputs
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Low voltage interface support to graphics device
• Offered in a 64-pin LQFP package
The CH7011 is a display controller device which
accepts a digital graphics input signal, and encodes and
transmits data to a TV output (analog composite, s-
video or RGB). The device accepts data over one 12-bit
wide variable voltage data port which supports five
different data formats including RGB and YCrCb.
The TV-Out processor will perform non-interlace to
interlace conversion with scaling and flicker filters, and
encode the data into any of the NTSC or PAL video
standards. The scaling and flicker filter is adaptive and
programmable to enable superior text display. Eight
graphics resolutions are supported up to 1024 by 768
with full vertical and horizontal underscan capability in
all modes. A high accuracy low jitter phase locked loop
is integrated to create outstanding video quality.
Support is provided for Macrovisionand RGB bypass
mode which enables driving a VGA CRT with the input
data.
LINE
MEMORY
D[11:0]
PIXEL DATA
DIGITAL
INPUT
INTERFACE
RGB-YUV
CONVERTER
TRUE SCALE
SCALING &
DEFLICKERING
ENGINE
YUV-RGB CONVERTER
NTSC/PAL
ENCODER
& FILTERS
Four
10-bit
DAC’s
GPIO[1:0]
SERIAL PORT REGISTER &
CONTROL BLOCK
SYSTEM CLOCK
PLL
TIMING & SYNC
GENERATOR
SPC SPD
RESET*
XCLK/XCLK*
H V XI/FIN XO CSYNC P-OUT BCO
Figure 1: Functional Block Diagram
CVBS (DAC3)
Y/G (DAC1)
C/R (DAC2)
CVBS/B
(DAC0)
ISET
201-0000-037 Rev 2.05, 6/6/2002
1




CH7011A pdf, 반도체, 판매, 대치품
CHRONTEL
Table 1. Pin Description
w6w4w-P.DiantaSheet4#UP.coinms Type
LQFP
36 1 Out
37 1 Out
38 1 Out
39 1 Out
42 1 In
43 1 In
46 1 Out
47 1 Out
48 1 Out
50 – 55,
58 – 63
12
In
CH7011A
Symbol Description
CVBS
Y/G
C/R
CVBS/B
XI / FIN
XO
P-OUT
BCO
C/H SYNC
D[11] - D[0]
Composite Video
This pin outputs a composite video signal capable of driving a
75 ohm doubly terminated load.
Luma / Green Output
This pin outputs a selectable video signal. The output is
designed to drive a 75 ohm doubly terminated load. The output
can be selected to be s-video luminance or green.
Chroma / Red Output
This pin outputs a selectable video signal. The output is
designed to drive a 75 ohm doubly terminated load. The output
can be selected to be s-video chrominance or red.
Composite Video / Blue Output
This pin outputs a selectable video signal. The output is
designed to drive a 75 ohm doubly terminated load. The output
can be selected to be composite video or blue.
Crystal Input / External Reference Input
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should
be attached between this pin and XO. However, an external
clock can drive the XI/FIN input.
Crystal Output
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should
be attached between this pin and XI / FIN. However, if an
external CMOS clock is attached to XI/FIN, XO should be left
open.
Pixel Clock Output
When the CH7011 is operating as a VGA to TV encoder in
master clock mode, this pin provides a pixel clock signal to the
VGA controller which is used as a reference frequency. The
output is selectable between 1X or 2X of the pixel clock
frequency. The output driver is driven from the DVDDV
supply. This output has a programmable tri-state. The
capacitive loading on this pin should be kept to a minimum.
Buffered Clock Output
This output pin provides a buffered clock output, driven by the
DVDD supply. The output clock can be selected using the BCO
register.
Composite / Horizontal Sync Output
This pin can be selected to output a TV composite sync, TV
horizontal sync, or a buffered version of the VGA horizontal
sync. The output is driven from the DVDD supply.
Data[11] through Data[0] Inputs
These pins accept the 12 data inputs from a digital video port
of a graphics controller. The levels are 0 to DVDDV, and the
VREF signal is used as the threshold level.
4 201-0000-037 Rev 2.05, 6/6/2002

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CH7011A 전자부품, 판매, 대치품
CHRONTEL
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CH7011A
XI/FIN,XO
P-OUT
BCO
2
XCLK,XCLK* 2
Clock
Driver
D[11:0] 12
Data
Latch,
Demux
H,V 2
VREF
H,V
Latch
24
3
TV-PLL
Timing
24
Scaling
Scan Conv
Flicker Filt
TV
Encode
Four
10-bit
DAC's
24
C/H SYNC
ISET
CVBS (DAC3)
Y/G (DAC 1)
C/R (DAC 2)
CVBS/B (DAC0)
Serial
Port
Control
2
GPIO[1:0]
AS
SPC
SPD
RESET*
Figure 3: TV Output Modes
201-0000-037 Rev 2.05, 6/6/2002
7

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CH7011A

Chrontel CH7011 TV Output Device

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