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PDF KB3700 Data sheet ( Hoja de datos )
| Número de pieza | KB3700 | |
| Descripción | Keyboard Controller | |
| Fabricantes | ENE | |
| Logotipo |  |
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KB3700
Keyboard Controller
Datasheet
Revision 0.1
July. 2006
ENE RESERVES THE RIGHT TO AMEND THIS DOCUMENT WITHOUT NOTICE AT ANY TIME. ENE ASSUMES
NO RESPONSIBILITY FOR ANY ERRORS APPEAR IN THE DOCUMENT, AND ENE DISCLAIMS ANY EXPRESS
OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF ENE PRODUCTS INCLUDING LIABILITY OR
WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, OR INFRINGEMENT OF ANY
PATENTS, COPYRIGHTS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
Copyright©2006, ENE Technology Inc. All rights reserved.
Headquarters
4F-1, No.9, Prosperity Rd.,
Science-based Industrial Park,
Hsinchu City, Taiwan, R.O.C
TEL: 886-3-6662888
FAX: 886-3-6662999
http://www.ene.com.tw
Taipei Office
9F, No.88, Bauchiau Rd.
Shindian City, Taipei,
Taiwan, R.O.C.
TEL: 886-2-89111525
FAX: 886-2-89111523
1 page  
KB3700 Keyboard Controller Datasheet
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Pulse Width Modulator (PWM)
5 built-in PWMs
Selectable clock sources: 1MHz/64KHz/4KHz/256Hz.
Configurable cycle time (up to 1 sec) and duty cycle.
Watchdog Timer (WDT)
32.768KHz input clock with 20-bit time scale.
8-bit watchdog timer interrupt and reset setting
General Purpose Timer (GPT)
Two 16-bit, two 8-bit general purpose timers with 32.768KHz resolution
General Purpose Wake-Up (GPWU)
All General Purpose Input pins can be configured to generate interrupts or
wake-up event.
General Purpose Input/Output (GPIO)
All I/O pins are bi-direction and configurable
All outputs can be optionally tri-stated
All inputs equipped with pull-up, high/low active, edge/level trigger selection
All GPIO pins are bi-direction, input and output.
Max. 43 GPIOs
Power Management
Sleep State: 8051 Program Counter (PC) stopped
Deep Sleep State: Stop all internal clocks. Target power consumption ~10uA.
Copyright©2006, ENE Technology Inc.
5
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KB3700 Keyboard Controller Datasheet
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4.1 Chip Architecture
4.1.1 Power Planes
There are 2 power planes in this chip. One is used for all logic, the other is used for Analog
parts (ADC).
4.1.2 Clock Domains
There are 4 clock domain in KB3700.
Flash chip interface clock. The clock default in 16MHz, and can be to 32MHz or 64MHz.
8051 / XBI use high clock (setting in CLKCFG, FF0Dh), ranges from 22~4MHz.
WDT uses 32.768KHz clock. WDT default use internal 32KHz clock. The WDTCFG bit 7
options can switch WDT clock to external 32KHz clock oscillator.
Other peripherals (GPWU, PWM,.) use low clock (setting in CLKCFG, FF0Dh), ranges
from 8~2MHz.
4.1.3 Reset Domains
This chip builds in power on reset. There is also a input reset signal (ECRST#) for global reset.
WDT reset can reset almost all logic, except WDT and GPIO modules. The WDT reset can be
set to only reset 8051 by EC register (PXCFG, FF14h).
There is additional 8051 reset source from EC register (PXCFG, FF14h).
4.2 GPIO
4.2.1 GPIO Functional Description
Multi-function pin Output Function Selection (FS) bit = 0, is set for GPIO Output Function,
and FS bit = 1, is set for Alternative Output. The alternative input function is enabled by Input
Enable register (IE), and is not affected by FS register.
Offset
Register
Abbreviation
Register Full Name
Bit Attr Description
GPIOFS00 GPIO 00~1B Output Function Selection (0: GPO, 1: Alternative Output)
00 00h: GPIOFS00 for GPIO00~07
GPIOFS08
~ 01h: GPIOFS08 for GPIO08~0F
GPIOFS10 7~0 R/W
03 02h: GPIOFS10 for GPIO10~17
GPIOFS18
03h: GPIOFS18 for GPIO18~1B
GPIOOE00 GPIO 00~1B Output Enable (0: Output Disable, 1: Output Enable)
GPIOOE08
10h: GPIOOE00 for GPIO00~07
10 11h: GPIOOE08 for GPIO08~0F
GPIOOE10
~ 12h: GPIOOE10 for GPIO10~17
GPIOOE18 7~0 R/W
15 13h: GPIOOE18 for GPIO18~1B
GPIOEOE0
14h: GPIOEOE0 for GPIOE0~7
GPIOEOE8
15h: GPIOEOE8 for GPIOE8~F (GPIOE9~A is N.A.)
20 GPIOD00 GPIO 00~1B Data Output
~ GPIOD08 7~0 R/W 20h: GPIOD00 for GPIO00~07
Def Bnk
0
0 FC
0
0
0
0
0 FC
0
0
0
FC
0
Copyright©2006, ENE Technology Inc.
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