PDF ISPXPGA Data sheet ( Hoja de datos )

Número de pieza	ISPXPGA
Descripción	ispXPGA Family
Fabricantes	Lattice Semiconductor
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No Preview Available ! www.DataSheet4U.com July 2008 Includes High- Performance, Low-Cost “E-Series” ispXPGA® Family Data Sheet DS1026 ■ Non-volatile, Inﬁnitely Reconﬁgurable • Instant-on - Powers up in microseconds via on-chip E2CMOS® based memory • No external conﬁguration memory • Excellent design security, no bit stream to intercept • Reconﬁgure SRAM based logic in milliseconds ■ High Logic Density for System-level Integration • 139K to 1.25M system gates • 160 to 496 I/O • 1.8V, 2.5V, and 3.3V VCC operation • Up to 414Kb sysMEM™ embedded memory ■ High Performance Programmable Function Unit (PFU) • Four LUT-4 per PFU supports wide and narrow functions • Dual ﬂip-ﬂops per LUT-4 for extensive pipelining • Dedicated logic for adders, multipliers, multiplex- ers, and counters ■ Flexible Memory Resources • Multiple sysMEM Embedded RAM Blocks – Single port, Dual port, and FIFO operation • 64-bit distributed memory in each PFU – Single port, Double port, FIFO, and Shift Register operation ■ Flexible Programming, Reconﬁguration, and Testing • Supports IEEE 1532 and 1149.1 • Microprocessor conﬁguration interface • Program E2CMOS while operating from SRAM ■ Eight sysCLOCK™ Phase Locked Loops (PLLs) for Clock Management • True PLL technology • 10MHz to 320MHz operation • Clock multiplication and division • Phase adjustment • Shift clocks in 250ps steps ■ sysIO™ for High System Performance • High speed memory support through SSTL and HSTL • Advanced buses supported through PCI, GTL+, LVDS, BLVDS, and LVPECL • Standard logic supported through LVTTL, LVCMOS 3.3, 2.5 and 1.8 • 5V tolerant I/O for LVCMOS 3.3 and LVTTL interfaces • Programmable drive strength for series termination • Programmable bus maintenance ■ Two Options Available • High-performance sysHSI (standard part number) • Low-cost, no sysHSI (“E-Series”) ■ sysHSI™ Capability for Ultra Fast Serial Communications • Up to 800Mbps performance • Up to 20 channels per device • Built in Clock Data Recovery (CDR) and Serialization and De-serialization (SERDES) Table 1. ispXPGA Family Selection Guide ispXPGA 125/E ispXPGA 200/E ispXPGA 500/E ispXPGA 1200/E System Gates 139K 210K 476K 1.25M PFUs 484 676 1764 3844 LUT-4s 1936 2704 7056 15376 Logic FFs 3.8K 5.4K 14.1K 30.7K sysMEM Memory 92K 111K 184K 414K Distributed Memory 30K 43K 112K 246K EBR 20 24 40 90 sysHSI Channels1 4 8 12 20 User I/O 160/176 160/208 336 496 Packaging 256 fpBGA 516 fpBGA2 256 fpBGA 516 fpBGA2 516 fpBGA2 900 fpBGA 680 fpSBGA2 900 fpBGA 1. “E-Series” does not support sysHSI. 2. FH516 package was converted to F516 via PCN# 09A-08. © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice. www.latticesemi.com 1 DS1026_14.1 1 page Lattice Semiconductor Fwiwgwu.rDeat2a.SihsepetX4UP.GcoAm PFU Control Logic OE PFUCLK0 PFUCLK1 CEB0 CEB1 SR WIN0 WIN1 WIN2 WIN3 LUT-4 COUT(r,c) COUT LUT-4 SUM CCG IN SEL0 XIN0 XIN1 XIN2 XIN3 LUT-4 SEL0 COUT LUT-4 SUM CCG IN SEL1 YIN0 YIN1 YIN2 YIN3 LUT-4 COUT LUT-4 SUM CCG IN SEL2 ZIN0 ZIN1 ZIN2 ZIN3 LUT-4 COUT LUT-4 SUM CCG IN SEL3 CIN(r,c) from COUT(r-1,c) ispXPGA Family Data Sheet COUT 4A S3 WLGW0 WIN2 WIN3 WLGW1 SEL0 4B S2 WLGX0 XIN2 XIN3 WLGX1 SEL1 4C S1 WLGY0 SYNC/ASYNC YIN2 YIN3 WLGY1 SEL2 4D S0 WLGZ0 ZIN2 ZIN3 WLGZ1 SEL3 D SQ R CLK/LE CE D SQ R CLK/LE CE DD SS QQ RR CLCKL/KLE/LE CCEE D SQ R CLK/LE CE DD SS QQ RR CLCKL/KLE/LE CCEE D SQ R CLK/LE CE DD SS QQ RR CLCKL/KLE/LE CCEE D SQ R CLK/LE CE OE W0 W1 X0 X1 Y0 Y1 Z0 Z1 5 5 Page Lattice Semiconductor Fwiwgwu.rDeat1a1S.heisept4XUP.coGmA PIO From sysHSI block From sysHSI block Feed-through (FT) From sysIO Input Clock (CLK) Input Clock Enable (ICEN) Input Set/Reset (ISR) Global Set/Reset(GSR) PIO Input (IN) Output Clock Enable (OCEN) Output Set/Reset (OSR) PIO Output Enable(OEN) Only for PIOs associated with sysHSI Blocks Delay DQ CLK/LE CE S R DQ CLK/LE CE S R DQ CLK/LE CE S R ispXPGA Family Data Sheet To Routing OUT0 OUT1 To sysIO Output To sysHSI block To sysHSI block Only for PIOs Associated with sysHSI Blocks To sysIO Output Enable PIO Input Enable (IEN) OE VLI Routing Resources The ispXPGA architecture contains a Variable-Length-Interconnect (VLI) routing technology connecting the PFUs, PICs, and EBRs in the device. There are four types of routing resources, Global Lines, Long Lines, General Inter- connect, and Local Lines forming the global routing structure. This allows a signal to be routed to any element in the device with the optimal delay. The Global Lines consist of global clock lines and a global set/reset line. These lines are routed to all elements in the device. They are speciﬁcally designed for high speed, predictable timing regardless of fan-out. The global clock lines can also be used as dedicated inputs. The Long Lines consist of Horizontal and Vertical Long Lines (HLL and VLL). The VLL and HLL are tri-statable lines spanning the entire device. These lines allow fast routing for high fan-out nets and general-purpose functions. The General Interconnect consists of Double and Deca Lines. The Double Lines connect up to three elements (two plus the driving element), while the Deca Lines connect up to eleven elements (ten plus the driving element). The Local Lines are extremely fast routing paths consisting of Feedback and Direct Connect Lines. The Feedback Lines are internal routing paths from the PFU outputs to the PFU inputs. The Direct Connect Lines connect all adja- cent elements. The Common Interface Block (CIB) provides the link between the logic element (PFU, PIC, or EBR) and the VLI Routing resources. The CIB is a switch matrix that can be programmed to connect virtually any routing resource to any input or output of the logic element. 11 11 Page

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