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ISPXPLD5000MX 데이터시트 PDF




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부품번호 ISPXPLD5000MX 기능
기능 eXpanded Programmable Logic Device XPLD
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ISPXPLD5000MX 데이터시트, 핀배열, 회로
ispXPLDTM 5000MX Family
www.DataSheet4U.com
3.3V, 2.5V and 1.8V In-System Programmable
eXpanded Programmable Logic Device XPLD™ Family
March 2006
Data Sheet
Features
Flexible Multi-Function Block (MFB)
Architecture
• SuperWIDE™ logic (up to 136 inputs)
• Arithmetic capability
• Single- or Dual-port SRAM
• FIFO
• Ternary CAM
sysCLOCK™ PLL Timing Control
• Multiply and divide between 1 and 32
• Clock shifting capability
• External feedback capability
sysIO™ Interfaces
• LVCMOS 1.8, 2.5, 3.3V
– Programmable impedance
– Hot-socketing
– Flexible bus-maintenance (Pull-up, pull-
down, bus-keeper, or none)
– Open drain operation
• SSTL 2, 3 (I & II)
• HSTL (I, III, IV)
• PCI 3.3
• GTL+
• LVDS
• LVPECL
• LVTTL
Table 1. ispXPLD 5000MX Family Selection Guide
Expanded In-System Programmability (ispXP™)
• Instant-on capability
• Single chip convenience
• In-System Programmable via IEEE 1532
Interface
• Infinitely reconfigurable via IEEE 1532 or
sysCONFIG™ microprocessor interface
• Design security
High Speed Operation
• 4.0ns pin-to-pin delays, 300MHz fMAX
• Deterministic timing
Low Power Consumption
• Typical static power: 20 to 50mA (1.8V),
30 to 60mA (2.5/3.3V)
• 1.8V core for low dynamic power
Easy System Integration
• 3.3V (5000MV), 2.5V (5000MB) and 1.8V
(5000MC) power supply operation
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL
interfaces
• IEEE 1149.1 interface for boundary scan testing
• sysIO quick configuration
• Density migration
• Multiple density and package options
• PQFP and fine pitch BGA packaging
• Lead-free package options
Macrocells
Multi-Function Blocks
Maximum RAM Bits
Maximum CAM Bits
sysCLOCK PLLs
tPD (Propagation Delay)
tS (Register Set-up Time)
tCO (Register Clock to Out Time)
fMAX (Maximum Operating Frequency)
System Gates
I/Os
Packages
ispXPLD 5256MX
256
8
128K
48K
2
4.0ns
2.2ns
2.8ns
300MHz
75K
141
256 fpBGA
ispXPLD 5512MX
512
16
256K
96K
2
4.5ns
2.8ns
3.0ns
275MHz
150K
149/193/253
208 PQFP
256 fpBGA
484 fpBGA
ispXPLD 5768MX ispXPLD 51024MX
768 1,024
24 32
384K
512K
144K
192K
22
5.0ns
5.2ns
2.8ns
3.0ns
3.2ns
3.7ns
250MHz
250MHz
225K
300K
193/317
317/381
256 fpBGA
484 fpBGA
484 fpBGA
672 fpBGA
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
5kmx_12.2




ISPXPLD5000MX pdf, 반도체, 판매, 대치품
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Cwwaws.cDaatadSihneget4FU.ocormWide Operation
In several modes it is possible to cascade adjacent MFBs to support wider operation. Table 2 details the different
cascading options. There are chains of MFBs in each device which determine those MFBs that are adjacent for the
purposes of cascading. Table 3 indicates these chains. The ispXPLD 5000MX design tools automatically cascade
blocks if required by a particular design.
Table 2. Cascading Modes For Wide Support
Mode
Logic
FIFO
CAM
Cascading Function
Input Width. Allows two MFBs to act as a 136-input block.
Arithmetic. Allow the carry chain to pass between two MFBs.
Memory Width Expansion. Allows MFBs to be cascaded for greater width support.
Memory Width Expansion. Allows up to four MFBs to be cascaded for greater width support.
Table 3. MFB Cascade Chain
Device
ispXPLD 5256MX
ispXPLD 5512MX
ispXPLD 5768MX
ispXPLD 51024MX
MFBs in Cascade Chain
ABCD
H -> G -> F -> E
ABCDEFGH
P→Ο→NMLKJI
DCBAXWVUTSRQ
EFGHIJKLMNOP
H G F E D C B A AF AE AD AC AB AA Z Y
IJKLMNOPQRSTUVWX
SuperWIDE Logic Mode
In logic mode, each MFB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic
product terms and four control product terms. The MFB has 68 inputs from the Global Routing Pool, which are
available in both true and complement form for every product term. It is also possible to cascade adjacent MFBs to
create a block with 136 inputs. The four control product terms are used for shared reset, clock, clock enable, and
output enable functions. Figure 3 shows the overall structure of the MFB in logic mode while Figure 4 provides a
more detailed view from the perspective of a macrocell slice.
4

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ISPXPLD5000MX 전자부품, 판매, 대치품
Lattice Semiconductor
Fwiwgwu.rDeat6a.SDheueat4lU-O.cRomPT Sharing Array
From PT0
ispXPLD 5000MX Family Data Sheet
From Carry
n-7 In
To I/O Block
PT OE
From PT1
PTSA Bypass To Macrocell
From PT2
From PT3
N To PTSA
To Macrocell
PT Clock
To Macrocell
PT Preset
From PT4
To Carry
n+7 Out
To Macrocell
PT Reset
Product Term Sharing Array
The Product Term Sharing Array (PTSA) consists of 32 inputs from the Dual-OR Array (Expandable PTSA OR) and
32 outputs directly to the macrocells. Each output is the OR term of any combination of the seven Expandable
PTSA OR terms connected to that output. Every Nth macrocell is connected to N-3, N-2, N-1, N, N+1, N+2 and
N+3 PTSA OR terms via a programmable connection. This wraps around the logic, for example, Macrocell 0 gets
its logic from 29, 30, 31, 0, 1, 2, 3. The Expandable PTSA OR used in conjunction with the PTSA allows wide func-
tions to be implemented easily and efficiently. Without using the Expandable PTSA OR capability, the greatest
number of product terms that can be included in a single function with one pass of delay is 35. Up to 160 product
terms can be included in a single function through the use of the expandable PTSA OR capability. Figure 7 shows
the graphical representation of the PTSA.
Figure 7. Product Term Sharing Array (PTSA)
PTSA OR 0
PTSA OR 1
PTSA OR 2
PTSA OR 3
Macrocell 0
Macrocell 1
Macrocell 2
PTSA OR 29
PTSA OR 30
PTSA OR 31
Macrocell 29
Macrocell 30
Macrocell 31
7

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ISPXPLD5000MX

eXpanded Programmable Logic Device XPLD

Lattice Semiconductor
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