WED3DG6466V-D1 Datasheet PDF - White Electronic Designs
| Part Number | WED3DG6466V-D1 | |
| Description | 512MB -64Mx64 SDRAM UNBUFFERED | |
| Manufacturers | White Electronic Designs | |
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Whitewww.datasheet4u.com Electronic Designs
WED3DG6466V-D1
-JD1
512MB – 64Mx64 SDRAM UNBUFFERED
FEATURES
PC100 and PC133 compatible
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full
Page
3.3V ± 0.3V Power Supply
144 Pin SO-DIMM JEDEC
• Package height option:
JD1: 31.75 mm (1.25”)
DESCRIPTION
The WED3DG6466V is a 64Mx64 synchronous DRAM
module which consists of eight 64Mx8 SDRAM components
in TSOP II package, and one 2K EEPROM in an 8 pin
TSSOP package for Serial Presence Detect which
are mounted on a 144 pin SO-DIMM multilayer FR4
Substrate.
* This product is subject to change without notice.
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PINOUT
PIN FRONT PIN BACK PIN FRONT PIN BACK PIN BACK PIN BACK
1 VSS 2 VSS 49 DQ13 50 DQ45 97 DQ22 98 DQ54
3 DQ0 4 DQ32 51 DQ14 52 DQ46 99 DQ23 100 DQ55
5 DQ1 6 DQ33 53 DQ15 54 DQ47 101 VCC 102 VCC
7 DQ2 8 DQ34 55 VSS 56 VSS 103 A6 104 A7
9 DQ3 10 DQ35 57 NC 58 NC 105 A8 106 BA0
11 VCC 12 VCC 59 NC 60 NC 107 VSS 108 VSS
13 DQ4 14 DQ36 61 CKL0 62 CKE0 109 A9 110 BA1
15 DQ5 16 DQ37 63 VCC 64 VCC 111 A10 112 A11
17 DQ6 18 DQ38 65 RAS# 66 CAS# 113 VCC 114 VCC
19 DQ7 20 DQ39 67 WE# 68 NC 115 DQMB2 116 DQMB6
21 VSS 22 VSS 69 CS0# 70 A12 117 DQMB3 118 DQMB7
23 DQMB0 24 DQMB4 71 NC 72 NC 119 VSS 120 VSS
25 DQMB1 26 DQMB5 73 NC 74 CK1 121 DQ24 122 DQ56
27 VCC 28 VCC 75 VSS 76 VSS 123 DQ25 124 DQ57
29 A0 30 A3 77 NC 78 NC 125 DQ26 126 DQ58
31 A1 32 A4 79 NC 80 NC 127 DQ27 128 DQ59
33 A2 34 A5 81 VCC 82 VCC 129 VCC 130 VCC
35 VSS 36 VSS 83 DQ16 84 DQ48 131 DQ28 132 DQ60
37 DQ8 38 DQ40 85 DQ17 86 DQ49 133 DQ29 134 DQ61
39 DQ9 40 DQ41 87 DQ18 88 DQ50 135 DQ30 136 DQ62
41 DQ10 42 DQ42 89 DQ19 90 DQ51 137 DQ31 138 DQ63
43 DQ11 44 DQ43 91 VSS 92 VSS 139 VSS 140 VSS
45 VCC 46 VCC 93 DQ20 94 DQ52 141 SDA 142 SCL
47 DQ12 48 DQ44 95 DQ21 96 DQ53 143 VCC 144 VCC
PIN NAMES
A0 – A12 Address Input (Multiplexed)
BA0-1
DQ0-63
CK0, CK1
Select Bank
Data Input/Output
Clock Input
CKE0
CS0
RAS#
CAS#
WE#
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
DQMB0-7
VCC
VSS
SDA
SCL
DNU
NC
DQM
Power Supply (3.3V)
Ground
Serial Data I/O
Serial Clock
Do Not Use
No Connect
July 2005
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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Whitewww.datasheet4u.com Electronic Designs
WED3DG6466V-D1
-JD1
AC TIMING PARAMETERS
Speed Grade
100MHz
Symbol
tCK
tCH
tCL
tIS
Parameter
Clock Period
Clock High Time Rated @1.5V
Clock Low Time
Input Setup Times
Address/ Command & CKE
Data
Min
10
3
3
2
2
Max
tIH
tAC
tOH
tOHZ
tCCD
tCBD
tCKE
tRP
tRAS
tRCD
tRRD
tRC
tDQD
tDWD
tMRD
tROH
tDQZ
tDQM
tDPL
tDAL
tSB
tSRX
tPDE
tCKSTP
tREF
tRFC
Input Hold Times
Address/Command & CKE
Data
Output Valid From Clock
CAS# Latency = 2 or 3,
LVTTL levels, Rated @ 50
pF all outputs switching
Output Hold From Clock Rated @ 50 pF (1.8 ns @ 0 pf)
Output Valid to Z
CAS to CAS Delay
CAS Bank Delay
CKE to Clock Disable
RAS Precharge Time
RAS Active Time
Activate to Command Delay (RAS to CAS Delay)
RAS to RAS Bank Activate Delay
RAS Cycle Time
DQM to Input Data Delay
Write Cmd. to Input Data Delay
Mode Register set to Active delay
Precharge to O/P in High Z
DQM to Data in High Z for read
DQM to Data mask for write
Data-in to PRE Command Period
Data-in to ACT (PRE) Command period (Auto precharge)
Power Down Mode Entry
Self Refresh Exit Time
Power Down Exit Set up Time
Clock Stop During Self Refresh or Power Down
Refresh Period
Row Refresh Cycle Time
1
1
6.0
(tco = 5.2)
3
39
1
1
1
20
50
20
20
70
0
0
3
CL
2
0
20
5
1
10
1
200
64
80.0
1. Access times to be measured w/input signals of 1 V/ns edge rate, 0.8 V to 2.0 V, tCO is clock to output with no load.
2. CL = CAS Latency
3. Data Masked on the same clock
4. Self refresh Exit is asynchronous, requiring 10 ns to ensure initiation. Self refresh exit is complete in 10 ns + tRC.
5. Timing is asynchronous. If tIS is not met by rising edge of CK then CKE is assumed latched on next cycle.
6. If the clock is stopped during self refresh or power down, 200 clocks are required before CKE is high.
Speed Grade
133MHz
Min Max
7.5
2.5
2.5
1.5
1.5
0.8
0.8
5.4
(tco = 4.6)
Units
ns
ns
ns
ns
ns
ns
ns
ns
2.7
2.7 7
1
1
1
20
45
20
15
67.5
0
0
3
CL
2
0
15
5
1
10
1
200
64
75.0
ns
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
tCK
tCK
tCK
tCK
tCK
tCK
ns
tCK
tCK
ns
tCK
tCK
ms
ns
Notes
1
2
3
4
5
6
July 2005
Rev. 3
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for WED3DG6466V-D1 electronic component. |
| Information | Total 7 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ WED3DG6466V-D1.PDF Datasheet ] | |
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