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WED3DG7264V-D1 데이터시트 PDF




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부품번호 WED3DG7264V-D1 기능
기능 512MB - 2x32Mx72 SDRAM
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WED3DG7264V-D1 데이터시트, 핀배열, 회로
Whitewww.datasheet4u.com Electronic Designs
WED3DG7264V-D1
PRELIMINARY*
512MB – 2x32Mx72 SDRAM, UNBUFFERED w/PLL
FEATURES
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full
Page
3.3V ± 0.3V Power Supply
144 Pin SO-DIMM
• D1: 31.75mm (1.25”)
DESCRIPTION
The WED3DG7264V is a 2x32Mx72 synchronous DRAM
module which consists of eighteen 32Mx8 stack SDRAM
components in TSOP II package, and one 2Kb EEPROM
in an 8 pin TSSOP package for Serial Presence Detect
which are mounted on a 144 pin SO-DIMM multilayer
FR4 Substrate.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PINOUT
PIN FRONT PIN
1 VSS 2
3 DQ0 4
5 DQ1 6
7 DQ2 8
9 DQ3 10
11 VCC 12
13 DQ4 14
15 DQ5 16
17 DQ6 18
19 DQ7 20
21 VSS 22
23 DQM0 24
25 DQM1 26
27 VCC 28
29 A0 30
31 A1 32
33 A2 34
35 VSS 36
37 DQ8 38
39 DQ9 40
41 DQ10 42
43 DQ11 44
45 VCC 46
47 DQ12 48
BACK
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
VSS
DQM4
DQM5
VCC
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VCC
DQ44
PIN FRONT PIN
49 DQ13 50
51 DQ14 52
53 DQ15 54
55 VSS 56
57 CB0 58
59 CB1 60
61 CLK0 62
63 VCC 64
65 RAS# 66
67 WE# 68
69 CS0# 70
71 CS1# 72
73 NC 74
75 VSS 76
77 CB2 78
79 CB3 80
81 VCC 82
83 DQ16 84
85 DQ17 86
87 DQ18 88
89 DQ19 90
91 VSS 92
93 DQ20 94
95 DQ21 96
BACK
DQ45
DQ46
DQ47
VSS
CB4
CB5
CKE0
VCC
CAS#
CKE1
A12
NC
NC
VSS
CB6
CB7
VCC
DQ48
DQ49
DQ50
DQ51
VSS
DQ52
DQ53
PIN FRONT PIN
97 DQ22 98
99 DQ23 100
101 VCC 102
103 A6 104
105 A8 106
107 VSS 108
109 A9 110
111 A10 112
113 VCC 114
115 DQM2 116
117 DQM3 118
119 VSS 120
121 DQ24 122
123 DQ25 124
125 DQ26 126
127 DQ27 128
129 VCC 130
131 DQ28 132
133 DQ29 134
135 DQ30 136
137 DQ31 138
139 VSS 140
141 SDA 142
143 VCC 144
BACK
DQ54
DQ55
VCC
A7
BA0
VSS
BA1
A11
VCC
DQM6
DQM7
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VCC
PIN NAMES
A0 – A12
BA0-1
DQ0-63
CLK0
CB0-7
CKE0,CKE1
CS0#,CS1#
RAS#
CAS#
WE#
DQM0-7
VCC
VSS
SDA
SCL
Address Input (Multiplexed)
Select Bank
Data Input/Output
Clock Input
Check Bit (Data-In/Data-Out)
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
DQM
Power Supply (3.3V)
Ground
Serial Data I/O
Serial Clock
DNU Do Not Use
NC No Connect
* These pins are not used in this module.
** These pins should be NC in the system which does
not support SPD.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 4
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com




WED3DG7264V-D1 pdf, 반도체, 판매, 대치품
Whitewww.datasheet4u.com Electronic Designs
WED3DG7264V-D1
PRELIMINARY
Parameter
Operating Current
(One bank active)
Precharge Standby Current
in Power Down Mode
Active Standby Current in
Power-Down Mode
Operating Current (Burst mode)
Refresh Current
Self Refresh Current
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
OPERATING CURRENT CHARACTERISTICS
VCC = 3.3V ±0.3V, 0°C ≤ TA ≤ +70°C
Version
Symbol
ICC1
ICC2
Conditions
Burst Length = 1
tRC ≤ tRC(min)
IOL = 0mA
CKE ≤ VIL(max), tCC = 10ns
100/133
1,620
35
ICC3 CKE ≥ VIL(max), tCC = 10ns
540
ICC4 Io = mA
Page burst
4 Banks activated
tCCD = 2CK
ICC5 tRC ≥ tRC(min)
ICC6 CKE ≤ 0.2V
1,800
3,600
110
Units
mA
mA
mA
mA
mA
mA
Note
1
1
2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 4
4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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WED3DG7264V-D1 전자부품, 판매, 대치품
Whitewww.datasheet4u.com Electronic Designs
WED3DG7264V-D1
PRELIMINARY
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VCC, VCCQ = +3.3V; = 25°C; pin under test biased at
1.4V. f = 1 MHz, TA
3. IDD is dependent on output loading and cycle rates.Specified values are obtained
with mini-mum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range (0°C ≤ ≤ 70°C) is TA ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (VCC and VCCQ
must be powered up simultaneously. VSS and VSSQ must be at same potential.) The
two AUTO REFRESH command wake-ups should be repeated any time the tREF
refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must
transit between VIH and VIL (or between VIL and VIH) in a mono-tonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
10. tHZ defines the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V
crossover point. If the input transition time is longer than 1ns, then the timing is
referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point.
12. Other input signals are allowed to transition no more than once every two clocks
and are other-wise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum
cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on
any timing parameter.
18. The IDD current will increase or decrease in a proportional amount by the amount
the frequency is altered for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 7.5ns for 75/10 and 7.
22. VIH overshoot: VIH (MAX) = VCCQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one third of the cycle rate. VIL under-shoot: VIL (MIN) = -2V
for a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable clock is defined as a signal
cycling within timing constraints specified for the clock pin) during access or
precharge states (READ, WRITE, including tWR, and PRECHARGE commands).
CKE may be used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns
after the first clock delay, after the last WRITE is executed.
25. Precharge mode only.
26. JEDEC and PC100, PC133 specify three clocks.
27. tAC for 75/10/7 at CL = 3 with no load is 4.6ns and is guaranteed by design.
28. Parameter guaranteed by design.
29. For 75/10, CL = 3, tCK = 7.5ns; For 7, CL = 2, tCK = 7.5ns
30. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6
limit is actually a nominal value and does not result in a fail value.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 4
7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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512MB - 2x32Mx72 SDRAM

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