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기능 Analog Keyboard Encoder
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AN-426 데이터시트, 핀배열, 회로
www.datasheet4u.com
Using MAX II CPLDs as
Analog Keyboard Encoders
July 2006, Version 1.0
Application Note 426
Introduction
Keyboard encoders are a very common application for CPLDs. Typically
a processor, ASSP, or ASIC does not have enough pins for keypads or
keyboards. I/O expansion is a very common function for CPLDs and
allows a processor to decode a very large keyboard with very few I/Os.
Even though CPLDs like MAX® and MAX® II may have abundant
low-cost I/Os, decoding a keypad or keyboard with one I/O per switch
is not desirable. The advantage of decoding a keyboard with fewer wires
is that it reduces the number of wires going from a keypad to a main
circuit board or it reduces the complexity of a switch matrix in the
keyboard assembly. This application note explains how the resources of a
MAX II device can be used to decode a very large number of switches in
a keypad or keyboard with only two I/Os and a GND pin. The decoding
approach used works for as few as 4 switches and as many as 48 switches.
Keyboard
Decode Methods
The most common way to encode a switch with a CPLD is by using a
simple circuit that ties one end of the switch to GND and the other terminal
to VCC through a pull-up resistor, typically 10 KΩ. The switch and
resistor node are connected to any CPLD input pin. For a pushbutton
normally-open Single Pole, Single Throw (SPST) switch, the CPLD input
is normally a logic one and is a logic zero when the switch is pressed.
Figure 1 shows the circuit for a simple one CPLD I/O per switch hookup.
You can enhance this circuit by using a Schmitt trigger input buffer
available in the MAX II device. The Schmitt trigger input reduces
switching noise and makes switch debounce easier. Refer to AN 422:
Power Management in Portable Systems Using MAX II CPLDs to learn how
to integrate a power-up and power-down mechanism into the switch
decode circuit.
Altera Corporation
AN-426-1.0
1
Preliminary




AN-426 pdf, 반도체, 판매, 대치품
Using MAX II CPLDs as Analog Keyboard Encoders
www.datasheet4u.com
all four columns are scanned, a 16-bit register holds the logic value of all
the switches. This approach is able to detect single-switch and
multiple-switch combinations. When the register becomes all zeros, the
scan logic may go back to the idle state, driving the columns low to save
power.
The minimum ON pulse for a typical switch is > 3 ms. The typical human
minimum response time pressing and releasing a switch is
approximately 30 ms. The CPLD can easily scan the switch array in
< 10 µS. Therefore, it should not be a problem for the CPLD to decode a
switch before a user releases a switch.
f
Refer to AN 422 Power Management in Portable Systems Using MAX II
CPLDs to learn how to integrate a power-up and power-down
mechanism into the switch array decode circuit.
New Two-Wire
Keypad Decider
The pin-per-switch and row-and-column switch array approaches work
well, but they are not suitable for every application. They have some
disadvantages. The pin-per-switch approach has the following
drawbacks:
Requires many CPLD I/O pins for a large keyboard
Requires many parallel PCB traces to connect switches to the CPLD
Requires costly wide high-pin count connectors between the
membrane switch and the motherboard
Requires discrete resistors per switch
The row-and-column switch array approach can significantly reduce the
number of CPLD pins required and can reduce the number of wires
required to connect a membrane switch to a mother board. However, the
row-and-column switch array still has some disadvantages:
Requires two-layer PCB breakout due to orthogonal
row-and-column traces to connect switches
Requires more costly two-layer membrane switch
Receives only a small reduction in CPLD I/O pins for smaller
keyboard arrays
You can use an analog-to-digital converter to decode a switch array.
When a set of resistors connects in series between VCC and GND and a
switch is connected to each resistor tap and a common node, if a switch is
turned activated, the circuit generates a voltage proportional to the
switch location in the resistor stack. You can use the output of an
analog-to-digital converter to decode the pressed switch. The circuit for
this type of decode is shown in Figure 3.
4
Preliminary
Altera Corporation

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AN-426 전자부품, 판매, 대치품
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New Two-Wire Keypad Decider
The values of R2 to R5 are set such that the total resistance
R2 + R3 + ... + R4 + R5 is shorted to Sense through switch 1. The
total resistance has to be low enough that the Sense voltage is less
than the input low threshold of the Sense input of the MAX II
device, as shown in Equation 1.
(1) VSense = (---R----2(---R-+---2--R--+--3---R--+--3-----+---+-----R--+--4--R--+--4---R--+--5---R--+--5---R)----6---) < VIL
The minimum resistance of R1 must be large enough to allow for the
drive of the MAX II PreCharge output, as shown in Equation 2.
(2) -(--V---R-C---1-C----<----I--V-O---OH----H---)-
In addition, the Sense drive must be strong enough when switch 1
is shorted, as shown in Equation 3.
(3) -(--V---R-C---1-C----<-----I-V-O---O-L---L---)
Resistor stack R1-R5 and capacitor C1 forms an RC time constant
when Sense is tri-stated and no switch is pressed, as shown in
Equation 4.
(4) τ = (R1 + R2 + R3 + R4 + R5) × C1
When a switch is pressed and Sense is low, the RC time constant
changes. If switch SW2 is pressed, then the RC time constant
becomes faster, as shown in Equation 5.
(5) τ = (R1 + R2) × C1
If switch SW4 is pressed, then the RC time constant becomes
(Equation 6):
(6) τ = (R2 + R3 + + R4 + R5) × C1
To determine the switch presses based on the time constant, use the
internal oscillator of the MAX II device. Because the MAX II internal
oscillator is only approximately 25% accurate but is consistent, the
measurement of the RC time constant must be done in two parts.
Altera Corporation
7
Preliminary

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부품번호상세설명 및 기능제조사
AN-426

Analog Keyboard Encoder

Altera
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