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NT512D72S8PB0G 데이터시트 PDF




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부품번호 NT512D72S8PB0G 기능
기능 184 pin Unbuffered DDR DIMM
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NT512D72S8PB0G 데이터시트, 핀배열, 회로
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
512MB, 256MB and 128MB
PC3200, PC2700 and PC2100
Unbuffered DDR DIMM
184 pin Unbuffered DDR DIMM
www.daBtaassheedeto4nu.DcoDmR400/333/266 256M bit B Die device
Features
• 184 Dual In-Line Memory Module (DIMM)
• Unbuffered DDR DIMM based on 256M bit die B device,
organized as either 32Mbx8 or 16Mbx16
• Performance:
PC3200 PC2700 PC2100
Speed Sort
5T 6K 75B Unit
DIMM CAS Latency
3 2.5 2.5
fCK Clock Frequency
200 166 133 MHz
tCK Clock Cycle
5 6 7.5 ns
fDQ DQ Burst Frequency 400 333 266 MHz
• Intended for 133, 166 and 200 MHz applications
• Inputs and outputs are SSTL-2 compatible
• VDD = VDDQ = 2.5V ± 0.2V (2.6V ± 0.1V for PC3200)
• SDRAMs have 4 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM CAS Latency: 2, 2.5, 3
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 7.8 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect EEPROM
• Gold contacts
• SDRAMs are packaged in TSOP packages
• “Green” packaging – lead free
Description
NT512D64S8HB0G, NT512D64S8HB1G, NT512D64S8HB1GY, NT512D72S8PB0G, NT256D64SH88B0G, NT256D64SH88B1G,
NT256D64SH88B1GY, NT256D72S89B0G and NT128D64SH4B1G are unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM
Dual In-Line Memory Modules (DIMM). NT512D64S8HB1GY and NT256D64SH88B1GY are packaged using lead free technology.
NT512D64S8HB0G, NT512D64S8HB1G and NT512D64S8HB1GY are 512MB modules organized as dual ranks using sixteen 32Mx8
TSOP devices. NT512D72S8PB0G has ECC and is organized as dual ranks using eighteen 32Mx8 TSOP devices. NT256D64SH88B0G,
NT256D64SH88B1G and NT256D64SH88B1GY are 256MB modules organized as single rank using eight 32Mx8 TSOP devices.
NT256D72S89B0G has ECC and is organized as single rank using nine 32Mx8 TSOP devices. NT128D64SH4B1G are 128MB modules,
organized as single rank using four 16Mx16 TSOP devices.
Depending on the speed grade, these DIMMs are intended for use in applications operating up to 200 MHz clock speeds and achieves
high-speed data transfer rates of up to 400 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation
type must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be
accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC.
REV 2.2
Aug 3, 2004
Preliminary
1
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.




NT512D72S8PB0G pdf, 반도체, 판매, 대치품
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Input/Output Functional Description
Symbol
CK0, CK1, CK2,
www.datasheCeKt04,uC.cKo1m, CK2
CKE0, CKE1
S0, S1
RAS, CAS, WE
VREF
VDDQ
BA0, BA1
A0 - A9
A10/AP
A11, A12
DQ0 - DQ63
DQS0 - DQS7,
DQS9 – DQS16
CB0 – CB7
DM0 – DM8
VDD, VSS
SA0 – SA2
SDA
SCL
VDDSPD
Type
(SSTL)
(SSTL)
(SSTL)
(SSTL)
Supply
Supply
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
Input
Supply
Supply
Polarity
Function
The system clock inputs. All address and command lines are sampled on the cross point of
Cross the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven
point from the clock inputs and output timing for read operations is synchronized to the input
clock.
Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low.
Active
High
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh
mode.
Enables the associated DDR SDRAM command decoder when low and disables the
Active command decoder when high. When the command decoder is disabled, new commands are
Low ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is
Active
Low
selected by S1.
When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to
be executed by the SDRAM.
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
- Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
- invoke auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,
auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low,
auto-precharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
- Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
Active
High
-
Active
High
Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.
Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte
mask by allowing input data to be written if it is low but blocks the write operation if it is high.
In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is
not used on x64 modules.
Power and ground for the DDR SDRAM input buffers and core logic
- Address inputs. Connected to either VDD or VSS on the system board to configure the Serial
Presence Detect EEPROM address.
- This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V DD to act as a pull-up.
- This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V DD to act as a pull-up.
Serial EEPROM positive power supply.
REV 2.2
Aug 3, 2004
Preliminary
4
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.

4페이지










NT512D72S8PB0G 전자부품, 판매, 대치품
NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Functional Block Diagram
1 Rank, 4 devices, 16Mx16 DDR SDRAMs
www.datasheet4u.com
S0
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
LDQS
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
D0
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
DQS5
DM5/DQS14
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS4
DM4/DQS13
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
CS
LDQS
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
D2
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS
LDQS
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
D1
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
DQS7
DM7/DQS16
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS6
DM6/DQS15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
CS
LDQS
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
D3
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
BA0-BA1
A0-A13
RAS
CAS
CKE0
WE
BA0-BA1 : SDRAMs D0-D3
A0-A13 : SDRAMs D0-D3
RAS : SDRAMs D0-D3
CAS : SDRAMs D0-D3
CKE : SDRAMs D0-D3
WE : SDRAMs D0-D3
SCL
WP
Serial PD
A0 A1 A2
SDA
SA0 SA1 SA2
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD is not equal to VDDQ.
* Clock Wiring
Clock Input SDRAMs
*CK0/CK0
NC
*CK1/CK1
2 SDRAMs
*CK2/CK2
2 SDRAMs
* Wire per Clock Loading Table/
Wiring Diagrams
VDDSPD
VDD/VDDQ
VREF
VSS
VDDID
SPD
D0-D3
D0-D3
D0-D3
Strap: see Note 4
REV 2.2
Aug 3, 2004
Preliminary
7
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.

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NT512D72S8PB0G

184 pin Unbuffered DDR DIMM

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