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PDF E1QS01 Data sheet ( Hoja de datos )
| Número de pieza | E1QS01 | |
| Descripción | ICE1QS01 | |
| Fabricantes | Infineon Technologies | |
| Logotipo |  |
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Datasheet, V1.4, 27 April 2004
www.datasheet4u.com
ICE 1QS01
Controller for Quasiresonant
Switch Mode Power Supplies
Supporting Low Power Standby
and Power Factor Correction
Power Management & Supply
Never stop thinking.
1 page  
Pinning
www.daPtaisnheet4uS.cyommbol
1 N.C.
2 PCS
3 RZI
4 SRC
5 OFC
6 GND
7 OUT
8 VCC
Function
Primary Current Simulation
Regulation and Zero Crossing Input
Soft-Start and Regulation Capacitor
Overvoltage Fault Comparator
Ground
Output
Supply Voltage
Pin Configuration (top view)
ICE1QS01
1 N.C.
2 PCS
3 RZI
4 SRC
VCC 8
OUT 7
GND 6
OFC 5
1
2 PCS
3 RZI
4 SRC
VCC
OUT
GND
OFC
8
7
6
5
Version 1.4
5
27 Apr 2004
5 Page 
ICE1QS01
SRC (Regulation and soft start capacitor)
The feedback capacitor is connected to pin SRC. The feedback voltage VSRC has two main func-
tions.
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voltage. If VPCS
external MOS
(which con-
transistor is
switched off.
Function II (MOS FET off time for frequency reduction): At low load the frequency is reduced by
ignoring zero crossing signals after the transformer demagnetization. VSRC determines the action of
the 4-bit up-down-counter which contains the number of zero crossings to be ignored. The content
of the up-down-counter is compared with the number of zero-current crossings of VRZI. If the
number of zero-current crossings in each period after the transformer demagnetization is equal to
the up-down-counter content the MOS is switched on. At low load conditions when VSRC is below
3.5V the counter is increased by one every 50 msec. The result is that the MOS transistor off-time
increases and duty cycle decreases. At high load conditions when VSRC is higher than 4.4V the
counter content is reduced by one every 50msec. So MOS transistor off-time will be reduced. With
this off-time regulation switching jitter can be eliminated.
The up-down-counter is immediately set to 0001 if a load jump occurs and VSRC exceeds 4.8 V.
This ensures that full power can be provided instantaneously.
The following table shows the SRC voltage range and the corresponding up-down counter action.
SRC voltage range
1: VSRC< 3.5V
2: 3.5<VSRC<4.4
3: VSRC>4.4
4: VSRC> 4.8
up-down-counter action
count forward
stop count
count backward
set up-down-counter to1
The information provided by VSRC is stored in two independent flip flops. An internal timer creates a
trigger pulse with a period of 50 msec. Every time the pulse occures the up-down counter checks
the status flip flops and acts depending on the flip flop information. After this pulse the flip flops are
reset. So change of voltage range is noticed by the logic only once during the 50 ms period. In the
diagram below the behaviour of the up-down counter is depicted in more detail.
D ia g ram 1
tim e r p u lse tp
VSRC
4.5 V
tp tp
50 m sec
tp
tp tp
tp tp tp
tp
3.5 V
status of
up-dow n n
n+1
n+1
n+1
n+1
n+1
n
n-1
n -2
n -3
c o u n te r
Version 1.4
11
27 Apr 2004
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet E1QS01.PDF ] | |
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