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PDF AD7984 Data sheet ( Hoja de datos )
| Número de pieza | AD7984 | |
| Descripción | 1.33 MSPS PulSAR 10.5 mW ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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18-Bit, 1.33 MSPS PulSAR 10.5 mW
ADC in MSOP/QFN
AD7984
www.daFtaEsAhTeeUt4RuE.cSom
18-bit resolution with no missing codes
Throughput: 1.33 MSPS
Low power dissipation: 10.5 mW at 1.33 MSPS
INL: ±2.25 LSB maximum
Dynamic range: 99.7 dB typical
True differential analog input range: ±VREF
0 V to VREF with VREF between 2.9 V to 5.0 V
Allows use of any input range
Easy to drive with the ADA4941
No pipeline delay
Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic
interface
Serial interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Ability to daisy-chain multiple ADCs and busy indicator
10-lead MSOP (MSOP-8 size) and 10-lead 3 mm × 3 mm QFN
(LFCSP), SOT-23 size
APPLICATIONS
Battery-powered equipment
Data acquisition systems
Medical instruments
Seismic data acquisition systems
APPLICATION DIAGRAM
2.9V TO 5V 2.5V
±10V, ±5V, ..
ADA4941
REF VDD VIO
IN+ SDI
AD7984 SCK
IN–
GND
SDO
CNV
1.8V TO 5V
3- OR 4-WIRE
INTERFACE
(SPI, CS
DAISY CHAIN)
Figure 1.
GENERAL DESCRIPTION
The AD7984 is an 18-bit, successive approximation, analog-to-
digital converter (ADC) that operates from a single power
supply, VDD. It contains a low power, high speed, 18-bit
sampling ADC and a versatile serial interface port. On the CNV
rising edge, the AD7984 samples the voltage difference between
the IN+ and IN− pins. The voltages on these pins usually swing
in opposite phases between 0 V and VREF. The reference voltage,
REF, is applied externally and can be set independent of the
supply voltage, VDD.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply.
The AD7984 is available in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
Table 1. MSOP, QFN (LFCSP) 14-/16-/18-Bit PulSAR® ADC
Type
100 kSPS
250 kSPS
400 kSPS to 500 kSPS
14-Bit
AD7940
AD79421
AD79461
16-Bit
AD7680
AD76851
AD76861
AD7683
AD76871
AD76881
AD7684
AD7694
AD76931
18-Bit
AD76911
AD76901
1 Pin-for-pin compatible.
≥1000 kSPS
AD79801
AD79831
AD79821
AD79841
ADC Driver
ADA4941-x
ADA4841-x
ADA4941-x
ADA4841-x
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
AD7984
TIMING SPECIFICATIONS
TA = −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise noted.1
Table 4.
www.daPtaarsahmeeet4teur.com
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 3 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
1 See Figure 2 and Figure 3 for load conditions.
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
Min
300
250
750
10
10.5
12
13
15
11.5
13
14
16
4.5
4.5
3
5
2
0
5
5
2
3
Typ Max Unit
500 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9.5 ns
11 ns
12 ns
14 ns
10 ns
15 ns
20 ns
ns
ns
ns
ns
ns
ns
ns
15 ns
500µA IOL
TO SDO
CL
20pF
500µA
IOH
1.4V
Figure 2. Load Circuit for Digital Interface Timing
X% VIO1
tDELAY
VIH2
VIL2
Y% VIO1
tDELAY
VIH2
VIL2
1FOR VIO ≤ 3.0V, X = 90, AND Y = 10; FOR VIO > 3.0V, X = 70, AND Y = 30.
2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
Figure 3. Voltage Levels for Timing
Rev. 0 | Page 5 of 24
5 Page 
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
www.daptoaisnhteuets4eud.caosmnegative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 22).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
Zero error is the difference between the ideal midscale voltage,
that is, 0 V, from the actual voltage producing the midscale
output code, that is, 0 LSB.
Gain Error
The first transition (from 100 ... 00 to 100 ... 01) should occur at
a level ½ LSB above nominal negative full scale (−4.999981 V
for the ±5 V range). The last transition (from 011 … 10 to
011 … 11) should occur for an analog voltage 1½ LSB below
the nominal full scale (+4.999943 V for the ±5 V range). The
gain error is the deviation of the difference between the actual
level of the last transition and the actual level of the first
transition from the difference between the ideal levels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD as follows:
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
AD7984
Noise-Free Code Resolution
Noise-free code resolution is the number of bits beyond which it is
impossible to distinctly resolve individual codes. It is calculated as
Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise)
and is expressed in bits.
Effective Resolution
Effective resolution is calculated as
Effective Resolution = log2(2N/RMS Input Noise)
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels. It is
measured with a signal at −60 dBF so that it includes all noise
sources and DNL artifacts.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components that are less than
the Nyquist frequency, including harmonics but excluding dc.
The value of SINAD is expressed in decibels.
Aperture Delay
Aperture delay is the measurement of the acquisition
performance and is the time between the rising edge of the
CNV input and when the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
Rev. 0 | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD7984.PDF ] | |
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