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PDF ATLV7 Data sheet ( Hoja de datos )
| Número de pieza | ATLV7 | |
| Descripción | Ultra Low Voltage Gate Arrays | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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ATLV
Features
• Specifically Designed for Battery Powered Applications
1.0 - 3.0 Volts and will Operate from 0.7 to 5.5 Volts
• Static Current Drain of <75 nA at 1.0 Volts
• 200 MHz Maximum Toggle Frequency for Flip Flop at 1.5 Volts
• 1.0 µ Drawn Gate Length CMOS Gate Arrays
• All Package Styles Offered Including TQFP and TAB
•www.daItamshpereot4vu.ecodmProduct Testability Using Serial Scan, Boundary Scan,
and JTAG
• Second Source Existing ASIC Design in Atmel's ATLV via Design
Translation. Improved Performance and Lower Cost
Description
The ATLV Series CMOS gate arrays employ 1.0 µ-drawn, double-level metal,
Si-gate, CMOS technology processed in Atmel's U.S.-based, advanced
manufacturing facility. The arrays utilize an enhanced channelless architecture
which results in greater than 50 percent usable gates.
Atmel's flexible design system uses industry design standards and is compatible
with popular CAD/CAE software and hardware packages. The customer can
start designing with the ATLV series today using existing CAD/CAE tools.
ATLV Array Organization
Device
Number
Raw
Gates
Routable
Gates
Max Pin
Count
Max I/O(1)
Pins
Gate(2)
Speed
ATLV2
ATLV3
ATLV5
ATLV7
2,000
3,000
5,000
7,000
1,400
1,600
2,800
4,400
44
68
84
100
36 1.3 ns
60 1.3 ns
76 1.3 ns
92 1.3 ns
ATLV10 10,000
6,600
120
112 1.3 ns
ATLV15 15,000
8,000
144
136 1.3 ns
ATLV20 22,000
12,000
160
152 1.3 ns
ATLV35 35,000
18,000
208
192 1.3 ns
Notes:
1. Absolute maximum I/O pins is maximum pin count minus 8. Additional power
and ground pins are assumed to be required to support simultaneous
switching outputs as pin count increases.
2. Nominal 2 input nand gate with a fan out of 2 at 1.5 volts, room temperature.
ATLV Series
Ultra Low
Voltage
Gate Arrays
ATLV2
ATLV3
ATLV5
ATLV7
ATLV10
ATLV15
ATLV20
ATLV35
0261B
1
1 page  
ATLV
CMOS Input Interface Characteristics
Interface
CMOS
Logic High
0.90 VDD
Logic Low
0.1 VDD
Switchpoint
VDD /2 Typical
Absolute Maximum Ratings*
www.datasheet4u.com
Operating Temperature .......................-40°C to +85°C
Storage Temperature ........................-65°C to +150°C
Voltage on Any Pin
with Respect to Ground ....................-2.0 V to +5.5 V1
Maximum Operating Voltage ...............................5.5 V
*NOTICE: Stresses beyond those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Notes:
1. Minimum voltage is -0.6 V dc which may undershoot to -2.0 V
for pulses of less than 20 ns. Maximum output pin voltage is
VDD + 0.75V dc which may overshoot to +7.0 V for pulses of less
than 20 ns.
1.5 Volt DC Characteristics
Applicable over recommended operating range from Ta = -40°C to +85°C, VDD = 1.0 V to 3.0 V (unless otherwise noted)
Symbol Parameter
Test Condition
Min Typ
Max Units
IIH Input Leakage High
VIN=VDD, VDD=1.8 V
1 x 10-5
10
µA
IIL Input Leakage Low
(no pull-up)
VIN=VSS, VDD=1.8 V
-10 -1 x 10-5
µA
IOZ
Output Leakage (no pull-up) VIN=VDD or VSS, VDD=3.6 V
-10 1 x 10-5
10
µA
IOS Output Short Circuit Current VDD=1.8 V, VOUT=VDD
(3 x Buffer)(2)
VDD=1.8 V, VOUT=VSS
5 25
-60 -25
60 mA
-5 mA
VIL CMOS Input Low Voltage
0.2 x VDD V
VIH CMOS Input High Voltage
VT CMOS Switching Threshold VDD=1.5 V, 25°C
VOL Output Low Voltage
IOL=as rated
Output buffer has
12 stages of drive capability
VDD=1.5 V
with 0.5 mA IOL per stage.
VOH
Output High Voltage
IOH=as rated
Output buffer has
VDD=1.5 V
12 stages of drive capability
with -0.5 mA IOH per stage.
IDD Static Current
Input Leakage Low
(no pull-up)
1.0 V
3.0 V
0.8 x VDD
0.75
0.2 x VDD
V
V
V
0.8 x VDD
V
< 75
< 1.0
nA
µA
Note: 2. This is the specification for the 3 x Output Buffer. Output short circuit current for other outputs will scale accordingly. Not more
than one output shorted at a time, for a maximum of one second, is allowed.
5
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet ATLV7.PDF ] | |
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