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CH5001A 데이터시트 PDF




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부품번호 CH5001A 기능
기능 CMOS COLOR DIGITAL VIDEO CAMERA
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CH5001A 데이터시트, 핀배열, 회로
CH5001A
CHRONTEL
CMOS Color Digital Video Camera
www.daFtaeshaeettu4ur.ceoms
• 352 x 288 active pixel array with color filters, 1/3 inch
lens format ¥
• Programmable formats CIF 352x288, QCIF 176x144,
CCIR601 704x288
• Digital output CCIR601 4:2:2 (8-bit or 16-bit)
• Multidimensional automatic shutter control
• Below 5 LUX sensitivity
• Programmable I2C Serial bus control:
- Frame rate: 30fps-1fps in eight steps
- Gamma correction
- Shutterspeed
- Analog gain
- 16 backlight compensation zones
- Black clamp level
- White balance adjustment
- Power down modes
• Stand-alone 25fps PAL operation with all automatic
features
• Single crystal operation: Video timing on-chip
• Single 5V power supply
• Less than 0.5 watt power dissipation
¥ Patent number x,xxx,xxx patents pending
Description
The CH5001 is a single chip active pixel CMOS color
video camera with digital video output in several formats.
Using sophisticated noise correction circuitry to minimize
fixed pattern noise and dark current effects, the CH5001
provides a supurb quality picture in a low cost device.
The CH5001 uses a proprietary autoshutter algorithm to
dynamically control the shutter time, analog gain, and
black clamp level, providing optimum picture and contrast
under all lighting conditions. The CH5001 also
incorporates extensive on-chip programmable digital
signal processing to maximize the usefulness of the device
in processor driven applications. This includes 16
programmable zones for backlight compensation,
allowing the user to adjust the image to their unique
lighting environment.
Additionally, at power-up the backlight compensation
zone, power-up condition, and direct A/D output modes
are selectable without IIC control by using the PUD pins.
Requiring a minimum of parts for operation, the CH5001
provides a low cost camera for the next generation video
conferencing, videophone, and surveillance products.
Photocell
352
Columns
Array
BG
GR
288
Rows
Row Decode
R
O Shutter
W Control
T
I
M
I
N
G
Color
Control
Gain
A/D
Black
Clamp
Matrix Gamma
Multiply Correct
RGB
to
YCrCB
Filter
Figure 1: Block Diagram
I 2C
BUS
Timing
&
Mode
Control
Output
Format
SD
SC
AS
HREF
PDP*
HS*
VS*
CLKOUT
Reset*
XI/Fin
XO
MONO
TOUT/TOUTB
OVR
Y[7:0]
C[7:0] PUD[6:0]
CRS
201-0000-032 Rev 3.0, 6/2/99
1
3




CH5001A pdf, 반도체, 판매, 대치품
CHRONTEL
CH5001A
Table 1. Pin Descriptions
Pin
21-14
Type
Out
Symbol
Y[7:0]
www.datas7h,e1e1t4, u2.2c,o3m4 Power
DVDD
4, 8, 24, 36 Power DGND
32-25 Out C[7:0]
33 Out CRS
23 Out CLKOUT
9 Out VS*
10 Out HS*
12 Out OVR
13 Out HREF
6 In SC
5 In/Out SD
2 In AS
3 In RESET*
38 In/Out XO
39 In
XI/FIN
Description
Video Output
Provides the luminance data of the digital video output.
Digital Supply Voltage
These pins supply the 5V power to the digital section of CH5001.
Digital Ground
Provides the ground reference for the digital section of CH5001. These
pins MUST be connected to the system ground.
Video Output
Chrominance data of the digital video output are provided by these
pins.
Cr Select
CRS specifies the CrCb data sequence. CRS is an alternating signal.
CRS=1 indicates that C[7:0] carry the Cr data. CRS=0 indicates C[7:0]
carry the Cb data.
Video Pixel Clock Output
This pin outputs a buffered clock signal which can be used to latch data
output by pins Y[7:0] and C[7:0].
Vertical Sync Output (active low)
Outputs a vertical sync pulse.
Horizontal Sync Output (active low)
Outputs a horizontal sync pulse.
Over Range
This pin is high when the A/D converter input is beyond the full scale
range of the A/D.
Horizontal Reference
Active video timing signal. This output is high when active data is being
output from the device, and low otherwise.
Serial Clock
IIC clock input pin.
Serial Data
IIC data input/output pin.
Chip Address Select (internal pullup)
This pin selects the IIC address for the device.
AS = 1 Address = 100 0101
AS = 0 Address = 100 0110
Chip Reset (active low, internal pullup)
Puts all registers into power-on default states. The state at pin SD must
be HIGH during reset for proper initialization.
Crystal Output
A 27 MHz (± 50 ppm, parallel resonance) crystal may be attached
between XO and XI/FIN.
Crystal Input or External input
A 27 MHz (± 50 ppm, parallel resonance) crystal should be attached
between XO and XI/FIN. An external CMOS compatible clock can be
connected to XI/FIN as an alternative.
4 201-0000-032 Rev 3.0, 6/2/99

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CH5001A 전자부품, 판매, 대치품
CHRONTEL
CH5001A
A/D Conversion:
The data out of the programmable sample and hold is input to an 8-bit A/D. The output of the A/D is sent to the
datapath section, and can alternatively be sent directly to the Y[7:0] pins. The A/D has an over-range output which
is available as an external pin.
Transformation to RGB domain:
www.datashEeeatc4hu.pcoixmel output from the A/D has been exposed to light which was filtered by one of three types of colored filter,
red, green or blue. To create RGB values for each pixel, four neighboring pixels are combined in different strengths
in a matrix multiplier. The gains used in the matrix multiplier are programmable via the CSCXX[7:0] registers.
Programmable Gamma correction of RGB signals:
The RGB signals are next applied to a gamma correction block with selectable gamma settings of 1.0, 1.6 and 2.2,
controlled via GAM[1:0]. Following gamma correction, a programmable offset is added to each term, via controls
ROS[4:0], GOS[4:0] and BOS[4:0].
Convert to the YCrCb domain:
A color space conversion is then applied to the gamma corrected RGB signals to convert to the Y, Cr, Cb domain.
The Cr and Cb gain can be independently adjusted in this block with the CRG and CBG controls.
Interpolate/Decimate data to desired resolution:
The output resolution is determined by the mode register bits M[2:0].
When a CCIR601 mode is selected (M[2:0] = 4,5), a signal compatible with Chrontel's CH7202 input will be gener-
ated. This entails interpolating the luminance signal by a factor of two, time multiplexing the CrCb signals, delay
matching the CrCb signal to the filtered Y signal, and selecting the 8-bit output mode (register 00h, bit 0).
When a CIF output is selected (M[2:0] = 1), the Cr,Cb resolution will be decimated by a factor of two in both hori-
zontal and vertical directions. This entails band-limiting the CrCb data, decimating in the horizontal direction, stor-
ing one line of decimated CrCb data and averaging the delayed line with the current line. This will position the
chrominance samples according to H.261 standards, and is register controlled (CVL, CHL). When CIF2 is selected,
the chrominance data is decimated in the horizontal direction only.
When QCIF output is selected (M[2:0] = 3), the Y resolution will be decimated by a factor of two in both horizontal
and vertical directions and the CrCb data will be decimated by a factor of four in both the horizontal and vertical
directions. This requires bandlimiting the Y and CrCb data, decimating in the horizontal direction. The Y data is
not be decimated in the vertical direction (since two lines have already been averaged in the matrix multiplier sec-
tion) but the CrCb data will generated a four line average in the vertical direction. When CIF2 is selected, the
chrominance data is decimated by four in the horizontal direction, and by two in the vertical direction.
Format the data stream for the desired type of output:
In addition to the selection of CCIR601 or the different CIF and QCIF modes, the output format can be selected
between 16-bit data (8-bit Y and 8-bit time multiplexed CrCb), and 8-bit data (time multiplexed Cb,Y,Cr,Y data at
twice the rate).
201-0000-032 Rev 3.0, 6/2/99
7

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부품번호상세설명 및 기능제조사
CH5001A

CMOS COLOR DIGITAL VIDEO CAMERA

Chrontel
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