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ZL30112 데이터시트 PDF




Zarlink Semiconductor에서 제조한 전자 부품 ZL30112은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 ZL30112 기능
기능 SLIC/CODEC DPLL
제조업체 Zarlink Semiconductor
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ZL30112 데이터시트, 핀배열, 회로
ZL30112
SLIC/CODEC DPLL
Data Sheet
Features
• Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or
www.datas1he9e.4t44u.cMomHz input
• Provides 2.048 MHz and 8.192 MHz output clocks
and an 8 kHz framing pulse
• Automatic entry and exit from freerun mode on
reference fail
• Provides DPLL lock and reference fail indication
• DPLL bandwidth of 29 Hz for all rates of input
references
• Less than 0.6 nsecpp intrinsic jitter on all output
clocks
• 20 MHz external master clock source: clock
oscillator or crystal
• Simple hardware control interface
November 2007
Ordering Information
ZL30112LDE1
32 Pin QFN* Tubes, Bake
& Drypack
*Pb Free Matte Tin
-40°C to +85°C
Applications
• Synchronizer for POTS SLIC/CODEC
• Rate convert NTR 8 kHz or GPON physical
interface clock to TDM clock
Description
The ZL30112 SLIC/CODEC DPLL contains a digital
phase-locked loop (DPLL), which provides timing and
synchronization for SLIC/CODEC devices.
The ZL30112 generates TDM clock and framing
signals that are phase locked to the input reference.
It helps ensure system reliability by monitoring its
reference for stability and by maintaining stable
output clocks during short periods when the
reference is unavailable.
REF
RST
OSCi
OSCo
Reference
Monitor
State Machine
Master
Clock
REF_FAIL
LOCK
DPLL
Mode
Control
C2o
C8o
F8ko
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2007, Zarlink Semiconductor Inc. All Rights Reserved.




ZL30112 pdf, 반도체, 판매, 대치품
Pin #
27
Name
REF
www.datas2h8eet4u.com IC
29 IC
30 IC
31 VDD
32 IC
33 GND
ZL30112
Data Sheet
I/O
Type
Description
I Reference Input. This input is used to synchronize the PLL. Synchronizes to
8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz.
I Internal Connection. Leave unconnected.
I Internal Connection. Connect to VDD.
I Internal Connection. Connect to VDD.
Positive Analog Supply Voltage. +3.3 VDC nominal.
I Internal Connection. Connect to GND.
Ground. 0 V. Package E-pad. This pin is internally connected to device GND. It
must be externally connected to GND.
4
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ZL30112 전자부품, 판매, 대치품
ZL30112
Data Sheet
Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and
based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is
dependent on the state of the ZL30112.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
www.daIntasthheeeAt4uu.tcoommatic Freerun mode, the DCO is free running at a frequency equal to the frequency that the DCO was
generating in Normal Mode.
Lock Indicator - the lock detector monitors if the output value of the phase detector is within the phase-lock-
window for a certain time. The selected phase-lock-window guarantees the stable operation of the LOCK pin with
maximum network jitter and wander on the reference input. If the DPLL goes into the Automatic Freerun mode, the
LOCK pin will initially stay high for 0.1 s. If at that point the DPLL is still in the Automatic Freerun mode, the LOCK
pin will go low.
3.4 Frequency Synthesizers
The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which
are synchronized to the input reference (REF).
The frequency synthesizer uses digital techniques to generate output clocks and advanced noise shaping
techniques to minimize the output jitter. The clock and frame pulse outputs have limited drive capability and should
be buffered when driving high capacitance loads.
3.5 Master Clock
The ZL30112 can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
7
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