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기능 Low Power RTC
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ISL12030 데이터시트, 핀배열, 회로
ISL12030
®
Real Time Clock with 50/60 Hz Clock and Alarms
Data Sheet
December 14, 2007
FN6617.0
Low Power RTC with 50/60 Cycle AC
Input, Alarms and Daylight Savings
www.Cdaotarshreeect4tui.oconm
The ISL12030 device is a low power real time clock with
50/60 AC input for timing synchronization, clock/calendar
registers, single periodic or polled alarms. There are 128
bytes of user SRAM.
The oscillator uses a 50/60 cycle sine wave input. The real
time clock tracks time with separate registers for hours,
minutes, and seconds. The calendar registers contain the
date, month, year, and day of the week. The calendar is
accurate through year 2100, with automatic leap year
correction and auto daylight savings correction.
Pinout
ISL12030
(8 LD SOIC)
TOP VIEW
NC 1
GND 2
AC 3
NC 4
8 VDD
7 IRQ
6 SCL
5 SDA
Features
• 50/60 Cycle AC as a Primary Clock Input for RTC Timing
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes, Seconds and tenths of a
Second
- Day of the Week, Day, Month and Year
• Auto Daylight Saving Time Correction
- Programmable Forward and Backward Dates
• Dual Alarms with Hardware and Register Indicators
- Hardware Single Event or Pulse Interrupt Mode
• 128 Bytes of User SRAM
• I2C Interface
- 400kHz Data Transfer Rate
• Pb-free (RoHS compliant)
Applications
• Utility Meters
• Control Applications
• Vending Machines
• White Goods
• Consumer Electronics
Ordering Information
PART NUMBER
(Note)
ISL12030IBZ*
PART MARKING
12030 IBZ
VDD RANGE
2.7V to 5.5V
TEMP RANGE
(°C)
-40 to +85
PACKAGE
(Pb-free)
8 Ld SOIC
PKG DWG #
M8.15
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.




ISL12030 pdf, 반도체, 판매, 대치품
ISL12030
I2C Interface Specifications Specifications apply for: VDD = 2.7 to 5.5V, TA = -40°C to +85°C,
unless otherwise stated. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 3) (Note 8) UNITS NOTES
CPIN
SDA and SCL Pin Capacitance
www.datasheet4u.com
fSCL
SCL Frequency
TA = +25°C, f = 1MHz,
VDD = 5V, VIN = 0V,
VOUT = 0V
tIN Pulse Width Suppression Time at Any pulse narrower than the
SDA and SCL Inputs
max spec is suppressed.
10 pF
400 kHz
50 ns
tAA SCL Falling Edge to SDA Output SCL falling edge crossing
Data Valid
30% of VDD, until SDA exits
the 30% to 70% of VDD
window.
900 ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VDD
during a STOP condition, to
SDA crossing 70% of VDD
during the following START
condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD
crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
crossing.
600
ns
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tHD:STO
tDH
tR
tF
Cb
START Condition Setup Time
SCL rising edge to SDA
falling edge. Both crossing
70% of VDD.
600
START Condition Hold Time
From SDA falling edge
crossing 30% of VDD to SCL
falling edge crossing 70% of
VDD.
600
Input Data Setup Time
From SDA exiting the 30% to
70% of VDD window, to SCL
rising edge crossing 30% of
VDD.
100
Input Data Hold Time
From SCL falling edge
crossing 30% of VDD to SDA
entering the 30% to 70% of
VDD window.
0
STOP Condition Setup Time
From SCL rising edge
crossing 70% of VDD, to SDA
rising edge crossing 30% of
VDD.
600
STOP Condition Hold Time
From SDA rising edge to
SCL falling edge. Both
crossing 70% of VDD.
600
Output Data Hold Time
From SCL falling edge
crossing 30% of VDD, until
SDA enters the 30% to 70%
of VDD window.
0
SDA and SCL Rise Time
From 30% to 70% of VDD. 20 + 0.1 x Cb
SDA and SCL Fall Time
From 70% to 30% of VDD. 20 + 0.1 x Cb
Capacitive loading of SDA or SCL Total on-chip and off-chip
10
ns
ns
ns
900 ns
ns
ns
ns
300 ns
300 ns
400 pF
7
7
7
4 FN6617.0
December 14, 2007

4페이지










ISL12030 전자부품, 판매, 대치품
ISL12030
General Description
The ISL12030 device is a low power real time clock with
50/60 AC input for timing synchronization, clock/calendar
registers, single periodic or polled alarms. There are 128
bytes of user SRAM.
The oscillator uses a 50/60 cycle sine wave input. The real
www.tdimataeschleoectk4ut.rcaocmks time with separate registers for hours,
minutes and seconds. The calendar registers contain the
date, month, year and day of the week. The calendar is
accurate through year 2100, with automatic leap year
correction and auto daylight savings correction.
The ISL12030’s alarm can be set to any clock/calendar
value for a match. Each alarm’s status is available by
checking the Status Register. The device also can be
configured to provide a hardware interrupt via the IRQ pin.
There is a repeat mode for the alarms allowing a periodic
interrupt every minute, every hour, every day, etc.
The ISL12030 devices are specified for VDD = 2.7V to 5.5V
Pin Descriptions
AC (AC Input)
The AC input is the main clock input for the real time clock. It
can be either 50Hz or 60Hz, sine wave. The preferred
amplitude is 2.5VP-P, although amplitudes >0.2 x VDD are
acceptable. An AC coupled (series capacitor) sine wave
clock waveform is desired as the AC clock input provides DC
biasing.
IRQ (Interrupt Output)
This pin provides an interrupt signal output. This signal
notifies a host processor that an alarm has occurred and
requests action. It is an open drain active LOW output.
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of
the device. The input buffer on this pin is always active (not
gated). It is disabled when the VDD supply drops below 2.7V.
Serial Data (SDA)
SDA is a bi-directional pin used to transfer data into and out
of the device. It has an open drain output and may be OR’ed
with other open drain or open collector outputs. The input
buffer is always active (not gated) in normal mode.
An open drain output requires the use of a pull-up resistor.
The output circuitry controls the fall time of the output signal
with the use of a slope controlled pull-down. The circuit is
designed for 400kHz I2C interface speeds.
VDD, GND
Chip power supply and ground pins. The device will operate
with a power supply from VDD = 2.7V to 5.5VDC. A 0.1µF
capacitor is recommended on the VDD pin to ground.
Functional Description
Power Supply Operation
The ISL12030 will function with inputs from VDD = 2.7V to
5.5VDC. If the VDD supply should drop below this, operation
to the specifications may be compromised, although the
SRAM memory will hold its values until VDD = 1.8V. Below
that, the entire device is not guaranteed to operate or retain
SRAM memory.
Power Failure Detection
The ISL12030 provides a Real Time Clock Failure Bit
(RTCF) to detect total power failure. It allows users to
determine if the device has powered up after having lost all
power to the device (VDD very near 0.0VDC).
Real Time Clock Operation
The Real Time Clock (RTC) maintains an accurate internal
representation of tenths of a second, second, minute, hour,
day of week, date, month and year. The RTC also has
leap-year correction. The clock also corrects for months
having fewer than 31 days and has a bit that controls 24
hour or AM/PM format. When the ISL12030 powers up after
the loss of VDD, the clock will not begin incrementing until at
least one byte is written to the clock register.
Alarm Operation
The alarm mode is enabled via the MSB bit. Single event or
interrupt alarm mode is selected via the IM bit. The standard
alarm allows for alarms of time, date, day of the week,
month and year. When a time alarm occurs in single event
mode, the IRQ pin will be pulled low and the corresponding
alarm status bit (ALM0 or ALM1) will be set to “1”. The
status bits can be written with a “0” to clear, or if the ARST
bit is set, a single read of the SRDC status register will
clear them.
The pulsed interrupt mode (setting the IM bit to “1”) activates
a repetitive or recurring alarm. Hence, once the alarm is set,
the device will continue to output a pulse for each occurring
match of the alarm and present time. The Alarm pulse will
occur as often as every minute (if only the nth second is set)
or as infrequently as once a year (if at least the nth month is
set). During pulsed interrupt mode, the IRQ pin will be pulled
LOW for 250ms and the alarm status bit (ALM0 or ALM1) will
be set to “1”.
General Purpose User SRAM
The ISL12030 provides 128 bytes of user SRAM. The SRAM
is volatile and will be lost or corrupted if VDD drops below
1.8V.
I2C Serial Interface
The ISL12030 has an I2C serial bus interface that provides
access to the control and status registers and the user
SRAM. The I2C serial interface is compatible with other
7 FN6617.0
December 14, 2007

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