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부품번호 TJA1080A 기능
기능 FlexRay transceiver
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TJA1080A 데이터시트, 핀배열, 회로
TJA1080A
FlexRay transceiver
Rev. 02 — 26 August 2008
Preliminary data sheet
www.datasheet4u.com
1. General description
The TJA1080A is a FlexRay transceiver, which is in line with the FlexRay electrical
physical layer specification V2.1 Rev. A (see Ref. 1). It is primarily intended for
communication systems from 1 Mbit/s to 10 Mbit/s, and provides an advanced interface
between the protocol controller and the physical bus in a FlexRay network.
The TJA1080A can be configured to be used as an active star transceiver or as a node
transceiver.
The TJA1080A provides differential transmit capability to the network and differential
receive capability to the FlexRay controller. It offers excellent EMC performance as well as
high ESD protection.
The TJA1080A actively monitors the system performance using dedicated error and
status information (readable by any microcontroller), as well as internal voltage and
temperature monitoring.
The TJA1080A supports the mode control as used in NXP Semiconductors TJA1054
(see Ref. 2) and TJA1041 (see Ref. 3) CAN transceivers.
The TJA1080A is the next step up from the TJA1080 FlexRay transceiver (Ref. 4). Being
fully pin compatible and offering the same excellent ESD protection, the TJA1080A also
features:
Improved power-on reset concept
Improved ElectroMagnetic Emission (EME)
Support of 70 ns minimum bit time
Improved bus error detection functionality
This makes the TJA1080A an excellent choice in any kind of FlexRay nodes.
See Section 14 for a detailed overview of differences between the TJA1080 and the
TJA1080A.
2. Features
2.1 Optimized for time triggered communication systems
I Compliant with FlexRay electrical physical layer specification V2.1 Rev. A (see Ref. 1)
I Automotive product qualification in accordance with AEC-Q100
I Data transfer up to 10 Mbit/s
I Support of 70 ns minimum bit time




TJA1080A pdf, 반도체, 판매, 대치품
NXP Semiconductors
TJA1080A
FlexRay transceiver
4. Block diagram
www.datasheet4u.com
VIO
4
TRXD0 11
VCC
19
TJA1080A
VBUF
20
TRXD1 10
VIO
SIGNAL
ROUTER
TXD
TXEN
BGE
STBN
EN
5
6
8
9
3
INPUT
VOLTAGE
ADAPTATION
VBAT
14
1 INH2
2 INH1
TRANS-
MITTER
18 BP
17
BM
BUS
FAILURE
DETECTION
RXD
ERRN
RXEN
7
13
12
VBAT
OUTPUT
VOLTAGE
ADAPTATION
RXDINT
STATE
MACHINE
WAKE 15
WAKE-UP
DETECTION
NORMAL
RXDINT RECEIVER
OVER-
TEMPERATURE
DETECTION
OSCILLATOR
UNDERVOLTAGE
DETECTION
Fig 1. Block diagram
16
GND
LOW-
POWER
RECEIVER
001aag892
TJA1080A_2
Preliminary data sheet
Rev. 02 — 26 August 2008
© NXP B.V. 2008. All rights reserved.
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TJA1080A 전자부품, 판매, 대치품
NXP Semiconductors
TJA1080A
FlexRay transceiver
6.1.3 Bus activity and idle detection
www.datasheet4u.com
The following mechanisms for activity and idle detection are valid for node and star
configurations in normal power modes:
If the absolute differential voltage on the bus lines is higher than |Vi(dif)det(act)| for
tdet(act)(bus), then activity is detected on the bus lines and pin RXEN is switched to LOW
which results in pin RXD being released:
If, after bus activity detection, the differential voltage on the bus lines is higher than
VIH(dif), pin RXD will go HIGH
If, after bus activity detection, the differential voltage on the bus lines is lower than
VIL(dif), pin RXD will go LOW
If the absolute differential voltage on the bus lines is lower than |Vi(dif)det(act)| for
tdet(idle)(bus), then idle is detected on the bus lines and pin RXEN is switched to HIGH.
This results in pin RXD being blocked (pin RXD is switched to HIGH or stays HIGH)
Additionally, in star configuration, activity and idle can be detected (see Figure 6 for state
transitions due to activity/idle detection in star configuration):
If pin TXEN is LOW for longer than tdet(act)(TXEN), activity is detected on pin TXEN
If pin TXEN is HIGH for longer than tdet(idle)(TXEN), idle is detected on pin TXEN
If pin TRXD0 or TRXD1 is LOW for longer than tdet(act)(TRXD), activity is detected on
pins TRXD0 and TRXD1
If pin TRXD0 and TRXD1 is HIGH for longer than tdet(idle)(TRXD), idle is detected on
pins TRXD0 and TRXD1
6.2 Operating modes in node configuration
The TJA1080A provides two control pins STBN and EN in order to select one of the
modes of operation in node configuration. See Table 3 for a detailed description of the pin
signalling in node configuration, and Figure 3 for the timing diagram.
All modes are directly controlled via pins EN and STBN unless an undervoltage situation
is present.
If VIO and (VBUF or VBAT) are within their operating range, pin ERRN indicates the status of
the error flag.
Table 3. Pin signalling in node configuration
Mode
STBN EN ERRN[1]
LOW
HIGH
Normal
HIGH HIGH error flag error flag
Receive-only HIGH LOW set
reset
Go-to-sleep
Standby
Sleep
LOW
LOW
LOW
HIGH error flag error flag
LOW set[2]
reset
X
RXEN
LOW
bus
activity
HIGH
bus
idle
wake flag wake
set[2]
flag
reset
RXD
LOW
bus
DATA_0
wake flag
set[2]
Transmitter INH1 INH2
HIGH
bus enabled
DATA_1 disabled
or idle
HIGH HIGH
wake
flag
reset
float[3]
float float
[1] Pin ERRN provides a serial interface for retrieving diagnostic information.
[2] Valid if VIO and (VBUF or VBAT) are present.
[3] If wake flag is not set.
TJA1080A_2
Preliminary data sheet
Rev. 02 — 26 August 2008
© NXP B.V. 2008. All rights reserved.
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