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PDF LTC2285 Data sheet ( Hoja de datos )
| Número de pieza | LTC2285 | |
| Descripción | 125Msps Low Power 3V ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
wwwn.daItanstheegert4aut.ecdomDual 14-Bit ADCs
n Sample Rate: 125Msps
n Single 3V Supply (2.85V to 3.4V)
n Low Power: 790mW
n 72.4dB SNR, 88dB SFDR
n 110dB Channel Isolation at 100MHz
n Flexible Input: 1VP-P to 2VP-P Range
n 640MHz Full Power Bandwidth S/H
n Clock Duty Cycle Stabilizer
n Shutdown and Nap Modes
n Data Ready Output Clock
n Pin Compatible Family
125Msps: LTC2283 (12-Bit), LTC2285 (14-Bit)
105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
n 64-Pin (9mm × 9mm) QFN Package
APPLICATIONS
n Wireless and Wired Broadband Communication
n Imaging Systems
n Spectral Analysis
n Portable Instrumentation
LTC2285
Dual 14-Bit, 125Msps
Low Power 3V ADC
DESCRIPTION
The LTC®2285 is a 14-bit 125Msps, low power dual 3V
A/D converter designed for digitizing high frequency,
wide dynamic range signals. The LTC2285 is perfect for
demanding imaging and communications applications
with AC performance that includes 72.2dB SNR and 82dB
SFDR for signals at the Nyquist frequency.
Typical DC specs include ±1.5LSB INL, ±0.6LSB DNL. The
transition noise is a low 1.3LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic.
A single-ended CLK input controls converter operation.
An optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
A data ready output clock (CLKOUT) can be used to latch
the output data.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
TYPICAL APPLICATION
ANALOG
INPUT A
+
INPUT
S/H
–
14-BIT
PIPELINED
ADC CORE
CLK A
CLK B
CLOCK/DUTY CYCLE
CONTROL
CLOCK/DUTY CYCLE
CONTROL
ANALOG
INPUT B
+
INPUT
S/H
–
14-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
OVDD
D13A
•••
D0A
OGND
OF
MUX
CLKOUT
OUTPUT
DRIVERS
OVDD
D13B
•••
D0B
OGND
2285 TA01
SNR vs Input Frequency,
–1dB, 2V Range
75
74
73
72
71
70
69
68
67
66
65
0
50 100 150 200 250 300 350
INPUT FREQUENCY (MHz) 2285 TA01b
2285fb
1
1 page  
LTC2285
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX
UNITS
VDD Analog Supply Voltage
wwwO.dVaDtDasheet4u.comOutput Supply Voltage
(Note 9)
(Note 9)
● 2.85
● 0.5
3
3
3.4
3.6
V
V
IVDD
PDISS
PSHDN
PNAP
Supply Current
Power Dissipation
Shutdown Power (Each Channel)
Nap Mode Power (Each Channel)
Both ADCs at fS(MAX)
Both ADCs at fS(MAX)
SHDN = H, OE = H, No CLK
SHDN = H, OE = L, No CLK
●
263 305
mA
●
790 915
mW
2 mW
15 mW
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
fs
tL
PARAMETER
Sampling Frequency
CLK Low Time
CONDITIONS
(Note 9)
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
MIN TYP MAX
●1
125
● 3.8 4 500
●3
4 500
UNITS
MHz
ns
ns
tH CLK High Time
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
● 3.8 4 500
●3
4 500
ns
ns
tAP Sample-and-Hold Aperture Delay
tD CLK to DATA Delay
CL = 5pF (Note 7)
0
● 1.4 2.7 5.4
ns
ns
tC CLK to CLKOUT Delay
DATA to CLKOUT Skew
CL = 5pF (Note 7)
(tD – tC) (Note 7)
● 1.4 2.7 5.4
● –0.6 0 0.6
ns
ns
tMD MUX to DATA Delay
Data Access Time After OE↓
CL = 5pF (Note 7)
CL = 5pF (Note 7)
● 1.4 2.7 5.4
● 4.3 10
ns
ns
BUS Relinquish Time
(Note 7)
●
3.3 8.5
ns
Pipeline Latency
5 Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 125MHz, input range = 2VP-P with differential
drive, unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and
11 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 125MHz, input range = 1VP-P with differential
drive. The supply current and power dissipation are the sum total for both
channels with both channels active.
Note 9: Recommended operating conditions.
2285fb
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5 Page 
LTC2285
APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
wwwS.diagtansahle-etto4-uN.coomise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is
the ratio between the RMS amplitude of the fundamen-
tal input frequency and the RMS amplitude of all other
frequency components at the ADC output. The output is
band limited to frequencies above DC to below half the
sampling frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodula-
tion distortion is defined as the ratio of the RMS value of
either input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or spuri-
ous noise that is the largest spectral component excluding
the input signal and DC. This value is expressed in decibels
relative to the RMS value of a full-scale input signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced
by 3dB for a full scale input signal.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD = 20log (V22 + V32 + V42 + ...Vn2) / V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the second
through nth harmonics. The THD calculated in this data
sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are ap-
plied to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at the sum and
difference frequencies of mfa ± nfb, where m and n = 0,
1, 2, 3, etc. The 3rd order intermodulation products are
Aperture Delay Time
The time from when CLK reaches midsupply to the in-
stant that the input signal is held by the sample and hold
circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
Crosstalk
Crosstalk is the coupling from one channel (being driven
by a full-scale signal) onto the other channel (being driven
by a –1dBFS signal).
CONVERTER OPERATION
As shown in Figure 1, the LTC2285 is a dual CMOS
pipelined multistep converter. The converter has six
pipelined ADC stages; a sampled analog input will result
in a digitized value five cycles later (see the Timing Dia-
gram section). For optimal AC performance the analog
inputs should be driven differentially. For cost sensitive
applications, the analog inputs can be driven single-ended
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11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC2285.PDF ] | |
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