PDF TMXA84622 Data sheet ( Hoja de datos )

Número de pieza	TMXA84622
Descripción	Ultramapper Full Transport
Fabricantes	Agere Systems
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No Preview Available ! Hardware Design Guide, Revision 1 February 21, 2003 TMXA84622 Ultramapper Full Transport 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1 www.datasheet4u.com 1 Introduction The last issue of this data sheet was November 27, 2002. A change history (since the last issue) is included in Section 12 Change History, on page 55. Red change bars have been installed on all text, figures, and tables that were added or changed. All changes to the text are highlighted in red. Changes within figures, and the figure title itself, are highlighted in red, if feasible. Formatting or grammatical changes have not been highlighted. Deleted sections, paragraphs, figures, or tables will be specifically mentioned. The documentation package for the TMXA84622 Full Transport 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1 sys- tem chip consists of the following documents: s The Register Description and the System Design Guide. These documents are available on a password-protected web- site. s The Ultramapper Full Transport Product Description and the Ultramapper Full Transport Hardware Design Guide (this document). These documents are available on the public website shown below (select Mappers/MUXes): http://www.agere.com/enterprise_metro_access/index.html This document describes the hardware interfaces to the Agere Systems TMXA84622 Ultramapper Full Transport device. Information relevant to the use of the device in a board design is covered. Pin descriptions, dc electrical characteristics, timing diagrams, ac timing parameters, packaging, and operating conditions are included. If the reader saves this document to disk and displays it using Acrobat ®Reader ®, clicking on any blue text will bring the reader to that reference point. Clicking on the back arrow (Go to previous View) in the toolbar of the Acrobat Reader will bring the reader back to the starting point. To contact Agere Systems, see the last page of this document or contact your Agere representative. 622/155 Mbits/s SONET/SDH ADM Front End LOPOH DS3/E3/DS2/DS1/E1 PDH Tributary Termination 6 High-Speed IF 622 Mb/STS-12/STM-4 155 Mb/STS-3/STM-1 Clock and Data 8 CDR Clock/Sync TMUX 6 Protection Link 622 Mb/STS-12/STM-4 155 Mb/STS-3/STM-1 Clock and Data 8 STS-12/ STM-4/ STS-3/ STM-1 CDR STSPP S T S X C Miscellaneous 24 JTAG MPU MCDR 5 JTAG IF 49 12 MPU IF (x3) STS-3/STM-1 Mate Interconnect LOPOH FRM (X3) x28/x21 DS1/J1/E1 CG 5 PLL IF SPEMPR (x3) (3-5) SPEMPR (x3) (0-2) STS-1 LT (x3) TPG/TPM (x3) x28/x21 VTMPR (x3) (x3) E13 M13 MUX MUX MRXC DS1/J1/E1 VT/TU DS2/E2 DS3/E3 3 1 3 1 X3 x28/x21 DS1/E1 DJA x6 DS3/E3 DJA System Interfaces 42 (x6) DS3/E3 (x3) STS-1 (x3) NSMI 24 (x3) STS-1 (Total of 3 STS-1 Max) 344 Low-Speed I/O Transport Modes 4DS1/J1/E1 (x86): x84/x63 + prot. 4DS2/E2 (X86): x63/x36 + prot. 11 E2, DS2, VC12 VC11 AIS Clocks 66 Power and GND pins not shown 22 TOAC POAC DS1XCLK, E1XCLK DS3XCLK, E3XCLK 10/10/02 Full Transport Figure 1-1. Ultramapper Full Transport Block Diagram and High-Level Interface Definition 1 page Hardware Design Guide, Revision 1 February 21, 2003 TMXA84622 Ultramapper Full Transport 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1 Figures List of Figures Page Figure 1-1. Ultramapper Full Transport Block Diagram and High-Level Interface Definition..................................................1 wwFFwiigg.duuarrteeas52he--11et..4UTu.MlctorUammX aLpVpDeSr FSuigllnTarlaRnsispeo/rFtaPllaTcikmaigneg Diagram (Top View) ..................................................................................6 ................................................................................................................. 36 Figure 5-2. TMUX LVDS Clock and Data Timing .................................................................................................................36 Figure 5-3. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 1)................................................................................37 Figure 5-4. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 0)................................................................................38 Figure 5-5. STS-3/STM-1 Mate Rise/Fall Timing .................................................................................................................38 Figure 5-6. STS-3/STM-1 Mate Clock and Data Timing.......................................................................................................38 Figure 5-7. TOAC, POAC Timing .........................................................................................................................................39 Figure 5-8. LOPOH Timing...................................................................................................................................................39 Figure 5-9. DS3/E3 Interface Diagram in M13/E13 Block ....................................................................................................40 Figure 5-10. NSMI Clock and Data Timing (STS-1 Mode) ...................................................................................................41 Figure 5-11. Shared Low-Speed Line Clock and Data Timing .............................................................................................41 Figure 7-1. Microprocessor Interface Synchronous Write Cycle—MPMODE Pin = 1 ..........................................................47 Figure 7-2. Microprocessor Interface Synchronous Read Cycle—MPMODE Pin = 1 ..........................................................48 Figure 7-3. Microprocessor Interface Asynchronous Write Cycle—MPMODE Pin = 0 ........................................................50 Figure 7-4. Microprocessor Interface Asynchronous Read Cycle—MPMODE Pin = 0 ........................................................51 Figure 10-1. Ultramapper Full Transport 909-Pin PBGA Balls and Dimensions ..................................................................54 Agere Systems Inc. 5 5 Page Hardware Design Guide, Revision 1 February 21, 2003 TMXA84622 Ultramapper Full Transport 622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1 Table 2-1. Package Pin Assignments (continued) Signal Name LINETXDATA[12] LINETXDATA[13] LINETXDATA[14] www.datasheet4u.LcoINmETXDATA[15] LINETXDATA[16] LINETXDATA[17] LINETXDATA[18] LINETXDATA[19] LINETXDATA[20] LINETXDATA[21] LINETXDATA[22] LINETXDATA[23] LINETXDATA[24] LINETXDATA[25] LINETXDATA[26] LINETXDATA[27] LINETXDATA[28] LINETXDATA[29] LINETXDATA[30] LINETXDATA[31] LINETXDATA[32] LINETXDATA[33] LINETXDATA[34] LINETXDATA[35] LINETXDATA[36] LINETXDATA[37] LINETXDATA[38] LINETXDATA[39] LINETXDATA[40] LINETXDATA[41] LINETXDATA[42] LINETXDATA[43] LINETXDATA[44] LINETXDATA[45] LINETXDATA[46] LINETXDATA[47] LINETXDATA[48] LINETXDATA[49] LINETXDATA[50] LINETXDATA[51] LINETXDATA[52] LINETXDATA[53] LINETXDATA[54] LINETXDATA[55] LINETXDATA[56] LINETXDATA[57] LINETXDATA[58] Pin B32 E28 B31 E27 H25 E26 D27 D26 F24 E24 F23 B27 E23 D23 H22 E22 F21 B23 C22 AA29 AB32 AD34 AA30 AC32 AE34 AB30 AF34 AC30 AC29 AG33 AE31 AC27 AE30 AJ33 AL31 AM33 AK30 AJ29 AM32 AN33 AK25 AK24 AK23 AP28 AP26 AP25 AN24 Table 2-1. Package Pin Assignments (continued) Signal Name LINETXDATA[59] LINETXDATA[60] LINETXDATA[61] LINETXDATA[62] LINETXDATA[63] LINETXDATA[64] LINETXDATA[65] LINETXDATA[66] LINETXDATA[67] LINETXDATA[68] LINETXDATA[69] LINETXDATA[70] LINETXDATA[71] LINETXDATA[72] LINETXDATA[73] LINETXDATA[74] LINETXDATA[75] LINETXDATA[76] LINETXDATA[77] LINETXDATA[78] LINETXDATA[79] LINETXDATA[80] LINETXDATA[81] LINETXDATA[82] LINETXDATA[83] LINETXDATA[84] LINETXDATA[85] LINETXDATA[86] LOPOHCLKIN LOPOHCLKOUT LOPOHDATAIN LOPOHDATAOUT LOPOHVALIDIN LOPOHVALIDOUT LOSEXT LP_INTN MODE0_PLL MODE1_PLL MODE2_PLL MPCLK MPMODE NC NC NC NC NC NC Pin AM22 AG18 AM19 AL18 AN19 AK11 AK16 AP17 AL15 AG8 AK5 AJ5 AK4 AH5 AG6 AL2 AF6 AJ3 N1 T8 L1 M3 M8 L4 H3 N8 E1 H5 B22 A21 D20 H19 E20 A20 AG27 W1 AJ31 AG30 AK31 G4 D2 N32 N33 P27 P31 R30 R31 Agere Systems Inc. Draft Copy Only 11 11 Page

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Número de pieza	Descripción	Fabricantes
TMXA84622	Ultramapper Full Transport	Agere Systems

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