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부품번호 FOD8001 기능
기능 3.3V Logic Gate Optocoupler
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FOD8001 데이터시트, 핀배열, 회로
March 2009
FOD8001
www.datasheet4u.com
High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Features
High Noise Immunity characterized by Common Mode
Rejection (CMR) and Power Supply Rejection (PSR)
specifications
– 20kV/µs Minimum Static CMR @ Vcm = 1000V
– 25kV/µs Typical Dynamic CMR @ Vcm = 1500V,
20MBaud Rate
– PSR in excess of 10% of the supply voltages
across full operating bandwidth
High Speed:
– 25Mbit/sec Date Rate (NRZ)
– 40ns max. Propagation Delay
– 6ns max. Pulse Width Distortion
– 20ns max. Propagation Delay Skew
3.3V and 5V CMOS Compatibility
Extended industrial temperate range, -40°C to 105°C
temperature range
Safety and regulatory pending approvals:
– UL1577, 3750 VACRMS for 1 min.
– IEC60747-5-2 (pending)
Applications
Industrial fieldbus communications
– Profibus, DeviceNet, CAN, RS485
Programmable Logic Control
Isolated Data Acquisition System
Description
The FOD8001 is a 3.3V/5V high-speed logic gate
Optocoupler, which supports isolated communications
allowing digital signals to communicate between sys-
tems without conducting ground loops or hazardous
voltages. It utilizes Fairchild’s patented coplanar packag-
ing technology, Optoplanar®, and optimized IC design to
achieve high noise immunity, characterized by high
common mode rejection and power supply rejection
specifications.
This high-speed logic gate optocoupler, packaged in a
compact 8-pin small outline package, consists of a high-
speed AlGaAs LED driven by a CMOS buffer IC coupled
to a CMOS detector IC. The detector IC comprises an
integrated photodiode, a high-speed transimpedance
amplifier and a voltage comparator with an output driver.
The CMOS technology coupled to the high efficiency of
the LED achieves low power consumption as well as
very high speed (40ns propagation delay, 6ns pulse
width distortion).
Related Resources
www.fairchildsemi.com/products/opto/
www.fairchildsemi.com/pf/FO/FOD0721.html
www.fairchildsemi.com/pf/FO/FOD0720.html
www.fairchildsemi.com/pf/FO/FOD0710.html
Functional Schematic
VDD1 1
8 VDD2
VI 2
7 NC
* 3 6 VO
GND1 4
5 GND2
*: Pin 3 must be left unconnected
©2008 Fairchild Semiconductor Corporation
FOD8001 Rev. 1.0.2
Truth Table
VI LED
H OFF
L ON
VO
H
L
www.fairchildsemi.com




FOD8001 pdf, 반도체, 판매, 대치품
Switching Characteristics (Apply over all recommended conditions, typical value is measured at
VDD1 = VDD2 = +3.3V, VDD1 = +3.3V and VDD2 = +5.0V, VDD1 = +5.0V and VDD2 = +3.3V, VDD1 = VDD2 = +5.0V, TA = 25°C)
Symbol Parameter
Test Conditions
Min. Typ. Max. Unit
tPHL Propagation Delay Time to
Logic Low Output
CL = 15pF
w w w . dtPLaH t Pa rospaghatioen Deelat y T4imue to. c o CLm= 15pF
Logic High Output
25 40 ns
25 40 ns
PWD
tPSK
tR
tF
|CMH|
|CML|
CPDI
Pulse Width Distortion,
| tPHL – tPLH |
Data Rate
Propagation Delay Skew
Output Rise Time (10%–90%)
Output Fall Time (90%–10%)
Common Mode Transient
Immunity at Output High
Common Mode Transient
Immunity at Output Low
Input Dynamic Power
Dissipation Capacitance(9)
PWD = 40ns, CL = 15pF
CL = 15pF(7)
VI = VDD1, VO > 0.8 VDD1,
VCM = 1000V(8)
VI = 0V, VO < 0.8V,
VCM = 1000V(8)
2 6 ns
25 Mb/s
20 ns
6.5 ns
6.5 ns
20 40
kV/µs
20 40
kV/µs
30 pF
CPDO Output Dynamic Power
Dissipation Capacitance(9)
3 pF
Notes:
7. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any
given temperature within the recommended operating conditions.
8. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of
the common mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient immunity
at output low is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal, Vcm, to
assure that the output will remain low.
9. Unloaded dynamic power dissipation is calculated as follows:
CPD x VDD x f + IDD + VPD where f is switched time in MHz.
©2008 Fairchild Semiconductor Corporation
FOD8001 Rev. 1.0.2
4
www.fairchildsemi.com

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FOD8001 전자부품, 판매, 대치품
Test Circuits
www.datasheet4u.comVDD1 = 3.3V
0.1µF
0V–3.3V
Pulse width = 40ns
Duty Cycle = 50%
1
2
3
4
8
7 0.1µF
VO
6
CL
5
VDD2 = 3.3V
Input
tPLH
VIN
tPHL
3.3V
50%
Output
90%
VOUT 10%
tR
VOH
50%
VOL
tF
Figure 13. Test Circuit for Propogation Delay Time and Rise Time, Fall Time
VDD1 = 3.3V
0.1µF
SW
AB
1
2
3
4
+–
VCM
8
7 0.1µF
VDD2 = 3.3V
VO
6
CL
5
GND
VOH
VOL
1kV VCM
Switching Pos. (A) VIN = 3.3V
0.8 x VDD
0.8V
Switching Pos. (B) VIN = 0V
CMH
CML
Figure 14. Test Circuit for Instantaneous Common Mode Rejection Voltage
©2008 Fairchild Semiconductor Corporation
FOD8001 Rev. 1.0.2
7
www.fairchildsemi.com

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부품번호상세설명 및 기능제조사
FOD8001

3.3V Logic Gate Optocoupler

Fairchild Semiconductor
Fairchild Semiconductor

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