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F801FA60 데이터시트, 핀배열, 회로
Freescale Semiconductor, Inc.
DSP56F801/D
Rev. 13.0, 02/2004
56F801
www.datasheet4u.com
Technical Data
56F801 16-bit Hybrid Controller
• Up to 30 MIPS operation at 60MHz core
frequency
• Up to 40 MIPS operation at 80MHz core
frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
• Hardware DO and REP loops
• 6-channel PWM Module
• Two 4-channel, 12-bit ADCs
• Serial Communications Interface (SCI)
• 8K × 16-bit words Program Flash
• 1K × 16-bit words Program RAM
• 2K × 16-bit words Data Flash
• 1K × 16-bit words Data RAM
• 2K × 16-bit words Boot Flash
• Serial Peripheral Interface (SPI)
• General Purpose Quad Timer
• JTAG/OnCETM port for debugging
• On-chip relaxation oscillator
• 11 shared GPIO
• 48-pin LQFP Package
6
PWM Outputs
Fault Input
A/D1
4 A/D2 ADC
4 VREF
PWMA
RESET
IRQA
6
JTAG/
OnCE
Port
VCAPC VDD
24
VSS
5*
VDDA
VSSA
Digital Reg Analog Reg
Low Voltage
Supervisor
Interrupt
Controller
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
Quad Timer C
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
Quad Timer D
Boot Flash
3
or GPIO
2048 x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
SCI0
or
2 GPIO
COP/
Watchdog
Application-
SPI Specific
4
or
GPIO
Memory &
Peripherals
••
PAB
PDB
XDB2
CGDB
• • •XAB1
XAB2
INTERRUPT
IPBB
CONTROLS CONTROLS
16 16
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
IPBus Bridge
(IPBB)
16-Bit
56800
Core
PLL
Clock Gen
or Optional
Internal
Relaxation Osc.
*includes TCS pin which is reserved for factory use and is tied to VSS
Figure 1. 56F801 Block Diagram
GPIOB3/XTAL
GPIOB2/EXTAL
© Motorola, Inc., 2004. All rights reserved.
For More Information On This Product,
Go to: www.freescale.com




F801FA60 pdf, 반도체, 판매, 대치품
Freescale Semiconductor, Inc.
and separate top and bottom output polarity control. The up-counter value is programmable to support a
continuously variable PWM frequency. Both edge- and center-aligned synchronous pulse width control (0%
to 100% modulation) are supported. The device is capable of controlling most motor types: ACIM (AC
Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and
Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection and cycle-by-
www.datashceyetc4lue.cocmurrent limiting with sufficient output drive capability to directly drive standard opto-isolators. A
“smoke-inhibit”, write-once protection feature for key parameters is also included. The PWM is double-
buffered and includes interrupt control to permit integral reload rates to be programmable from 1 to 16. The
PWM modules provide a reference output to synchronize the Analog-to-Digital Converters.
The 56F801 incorporates an 8 input, 12-bit Analog-to-Digital Converter (ADC). A full set of standard
programmable peripherals is provided that include a Serial Communications Interface (SCI), a Serial
Peripheral Interface (SPI), and two Quad Timers. Any of these interfaces can be used as General-Purpose
Input/Outputs (GPIO) if that function is not required. An on-chip relaxation oscillator provides flexibility
in the choice of either on-chip or externally supplied frequency reference for chip timing operations.
Application code is used to select which source is to be used.
1.3 State of the Art Development Environment
• Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-
use component-based software application creation with an expert knowledge system.
• The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system
cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a
complete, scalable tools solution for easy, fast, and efficient development.
1.4 Product Documentation
The four documents listed in Table 1 are required for a complete description and proper design with the
56F801. Documentation is available from local Motorola distributors, Motorola semiconductor sales
offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors.
Table 1. 56F801 Chip Documentation
Topic
Description
Order Number
DSP56800
Family Manual
DSP56F801/803/805/807
User’s Manual
56F801
Technical Data Sheet
56F801
Product Brief
DSP56F801
Errata
Detailed description of the 56800 family architecture, and
16-bit core processor and the instruction set
DSP56800FM/D
Detailed description of memory, peripherals, and interfaces DSP56F801-7UM/D
of the 56F801, 56F803, 56F805, and 56F807
Electrical and timing specifications, pin descriptions, and
package descriptions (this document)
DSP56F801/D
Summary description and block diagram of the 56F801 core, DSP56F801PB/D
memory, peripherals and interfaces
Details any chip issues that might be present
DSP56F801E/D
4 56F801 Technical Data
For More Information On This Product,
Go to: www.freescale.com

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F801FA60 전자부품, 판매, 대치품
Freescale Semiconductor, Inc.
Power and Ground Signals
2.2 Power and Ground Signals
Table 3. Power Inputs
No. of Pins Signal Name
Signal Description
www.datasheet4u.com4
1
VDD
VDDA
Power—These pins provide power to the internal structures of the chip, and should
all be attached to VDD.
Analog Power—This pin is a dedicated power pin for the analog portion of the chip
and should be connected to a low noise 3.3V supply.
No. of Pins
4
1
1
Table 4. Grounds
Signal Name
Signal Description
VSS
VSSA
TCS
GND—These pins provide grounding for the internal structures of the chip,
and should all be attached to VSS.
Analog Ground—This pin supplies an analog ground.
TCS—This Schmitt pin is reserved for factory use and must be tied to VSS for
normal use. In block diagrams, this pin is considered an additional VSS.
Table 5. Supply Capacitors and VPP
No. of Signal Signal
State
Pins Name Type During Reset
Signal Description
2 VCAPC Supply
Supply
VCAPC—Connect each pin to a 2.2 µFor greater bypass capacitor
in order to bypass the core logic voltage regulator (required for
proper chip operation). For more information, refer to Section 5.2.
2.3 Clock and Phase Locked Loop Signals
Table 6. PLL and Clock
No. of Signal
Pins Name
Signal
State
Type During Reset
Signal Description
1 EXTAL Input
GPIOB2 Input/
Output
Input
Input
External Crystal Oscillator Input—This input should be connected
to an 8MHz external crystal or ceramic resonator. For more
information, please refer to Section 3.5.
Port B GPIO—This multiplexed pin is a General Purpose I/O (GPIO)
pin that can be programmed as an input or output pin. This I/O can be
utilized when using the on-chip relaxation oscillator so the EXTAL pin
is not needed.
56F801 Technical Data
For More Information On This Product,
Go to: www.freescale.com
7

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