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부품번호 UP6210 기능
기능 Compact Dual Phase Synchronous Rectified Buck Controller
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UP6210 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Preliminary
uP6210
Compact Dual-Phase
Synchronous-Rectified Buck Controller
General Description
Features
The uP6210 is a compact dual-phase synchronous-rectified
Buck controller specifically designed to deliver high quality
output voltage for high power applications. This part is
capable of delivering up to 60A output current thanks to its
embedded bootstrapped drivers that support 12V + 12V
driving capability. The uP6210 features configurable gate
driving voltage for maximum efficiency and optimal
performance. The built-in bootstrap diode simplifies the
circuit design and reduces external part count and PCB
space.
The output voltage is precisely regulated to the reference
input that is dynamically adjustable by external voltage
divider. The uP6210 adopts DCR current sensing technique
for over current protection and droop control. The adjustable
current balance is achieved by RDS(ON) current sensing
technique.
This part features comprehensive protection functions
including over current protection, input/output under voltage
protection, over voltage protection and over temperature
protection.
Other features include adjustable soft start, adjustable
operation frequency, and quick response to step load
transient. With aforementioned functions, this part provides
customers a compact, high efficiency, well-protected and
cost-effective solutions. This part comes to VQFN4x4-24L
package.
Ordering Information
† Operate with Single Supply Voltage
† ±2.0% Over Line Voltage and Temperature
† Simple Single-Loop Voltage-Mode Control
† 12V Bootstrapped Drivers with Internal
Bootstrap Diode
† Adjustable Over Current Protection by DCR
Current Sensing
† Adjustable Current Balancing by RDS(ON) Current
Sensing
† Adjustable Operation Frequency form 50kHz to
1MHz Per Phase
† External Compensation
† Dynamic Output Voltage Adjustment
† Adjustable Soft Start
† VQFN4x4-24L Package
† RoHS Compliant and 100% Lead (Pb)-Free
Applications
† Middle-High End GPU Core Power
† High End Desktop PC Memory Core Power
† Low Output Voltage, High Power Density DC-DC
Converters
† Voltage Regulator Modules
Pin Configuration
Order Number Package Type
uP6210AQAG VQFN 4x4-24L
Remark
Note: uPI products are compatible with the current IPC/
JEDEC J-STD-020 and RoHS requirements. They are 100%
matte tin (Sn) plating and suitable for use in SnPb or Pb-
free soldering processes.
18 17 16 15 14 13
LG2 19
SW2 20
HG2 21
BOOT2 22
VID 23
RSET 24
GND
12 PSI
11 CSP
10 CSN
9 SS
8 EAP
7 FBRTN
123456
VQFN4x4-24L
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
1




UP6210 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
Preliminary
uP6210
Functional Pin Description
No. Pin Name Pin Function
Lower Gate Driver Output for Channel 2. Connect this pin to the gate of lower MOSFET. This
19 LG2 pin is monitored by the adaptive shoot-through protection circuitry to determine when the lower
MOSFET has turned off.
Switch Node for Channel 2. Connect this pin to the source of the upper MOSFET and the
20
SW2
drain of the lower MOSFET. This pin is used as the sink for the HG2 driver. This pin is also
monitored by the adaptive shoot-through protection circuitry to determine when the upper
MOSFET has turned off.
Upper Gate Driver Output for Channel 2. Connect this pin to the gate of upper MOSFET.
21
HG2
This pin is monitored by the adaptive shoot-through protection circuitry to determine when the
upper MOSFET has turned off.
22
BOOT2
Bootstrap Supply for the floating upper gate driver of channel 2. Connect the bootstrap
capacitor CBOOT between BOOT2 pin and the SW2 pin to form a bootstrap circuit.
23
VID
VID Input. This pin is used to adjust reference voltage. Logic high turns on the internal MOSFET
connected to RSET pin.
24
RSET
Reference Voltage Setting. This pin is an open drain output that is pulled low when VID = high.
Connect a resistor from this pin to REFIN pin to set the reference voltage.
Exposed Pad Power Ground. Tie this pin to the ground island/plane through the lowest impedance connection
GND
available.
Functional Block Diagram
VCC IOFS
PVCC
VREF
RSET
VID
FBRTN
REFIN
SS
EAP
FB
COMP
CSN
CSP
PSI
Reference
Voltage
POR
PWM1
Internal
Regulator
Gate
Control
Logic
Error
Amplifier
Power Saving
Setting
Current
Balance
PWM2
Gate
Control
Logic
Oscillator
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
RT/EN
GND
BOOT1
HG1
SW1
LG1
BOOT2
HG2
SW2
LG2
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UP6210 전자부품, 판매, 대치품
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Preliminary
uP6210
Functional Description
2 x L / RDC = RCSP x CCS
where L is the output inductor of the buck converter, RDC is
the parasitic resistance of the inductor, RCSP and CCS are
the external RC network for current sensing.
The GM amplifier will source a current ICSN to the CSN pin to
let its inputs virtually short circuit.
ICSN x RCSN = VCS
Therefore the output current signal ICSN can be expressed
as:
RT/EN or VCC POR.
Figure 5, and Figure 6 illustrate the OCP behaviors during
soft start and after soft start end respectively.
Current Balance
The uP6210 extracts phase currents for current balance by
parasitic on-resistance of the lower switches when turned
on as shown in Figure 5.
IOFS
ICSN
=
IOUT × RDC
2 × RCSN
The output current signal ICSN is used as droop tuning,
automatic phase reductin, and output over current protection.
Please see the related section for details.
SWx
ICS1
Sample
Current
& Hold ICS2 Balance
offset
voltage
uP6210
L
RDC
VOUT
RCSP
L
RDC
RCSP
CSP
CCS
CSN
RCSN
uP6210
GM
Amplifer
ICSN
Figure 4. Output Current Sensing of uP6210.
The sourcing capability of the GM amplifier is 100uA. It is
recommended to scale IAVG = 30uA at rated output current
and set the OCP current as twice the rated output current.
Take a 60A converter for example. Assume RDC = 2m,
select the sense resistor according to
RCSN
=
60A × 2m
2 × 30uA
=
2k
Over Current Protection
The sensed current signals are monitored for over current
protection. If ICSN is higher than 60uA, the over current
protection OCP is activated. Take the above case for
example, the OCP level is calculated as:
Figure 5. RDS(ON) Current Sensing Scheme
The GM amplifier senses the voltage drop across the lower
switch and converts it into current signal each time it turns
on. The sampled and held current is expressed as:
ICSX = ILX × RDS(ON) × 103 + 6.6uA
where ILX is the phase X current in Ampere, RDS(ON) is the on-
resistance of low side MOSFET in , 6.6uA is a constant
to compensate the offset voltage of the current sensing
circuit.
The uP6210 fine tunes the duty cycle of each channel for
current balance according to the sensed inductor current
signals as shown in Figure 6. If the current of channel 1 is
smaller than the current of channel 2, the uP6210 increases
the duty cycle of the corresponding phase to increase its
phase current accordingly, vice verse.
RAMP1
COMP
PWM1
RAMP2
ICS2
ICS1
PWM2
IOCP
=
2 × 60uA × 2k
2m
= 120A
The OCP is of latch-off type and can be reset by toggling
Figure 6. Current Balance Scheme of uP6210.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
7

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