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부품번호 | NJW1320 기능 |
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기능 | Video Switch / QFP48-P1 | ||
제조업체 | JRC | ||
로고 | |||
전체 12 페이지수
www.DataSheet4U.com
NJW1320
WIDE BAND VIDEO SWITCH WITH I2C BUS
s GENERAL DESCRIPTION
The NJW1320 is a Wide Band Video Switch with I2C BUS.The
NJW1320 includes switch of 4-input 3-output and 6dB amplifier. It is
suitable for Y, Pb, and Pr signal because frequency range is
50MHz.The NJW1320 includes external logic control terminals and
external logic discernment terminals. The NJW1320 is suitable for
PTV, DTV, PDP and other high quality AV systems.
s FEATURES
q Operating Voltage
9.0V
q 4-input 3-output 3-Circuits (Y, Pb, and Pr signal)
q Wide frequency range
0dB at 50MHz typ.
q Internal 6dB amplifier (Selectable Bypass or 6dB)
q External logic discernment terminal
q External logic control terminal
q Selectable slave address
q Power Save Circuit
q I2C BUS control
q Bi-CMOS Technology
q Package Outline
QFP48
s BLOCK DIAGRAM
Y IN1
Y IN2
Y IN3
Y IN4
6dB
6dB
Pb IN1
Pb IN2
Pb IN3
Pb IN4
6dB
6dB
6dB
Pr IN1
Pr IN2
Pr IN3
Pr IN4
6dB
6dB
6dB
PORT 0
PORT 1
PORT 2
PORT 3
VCC
GND
VREF
BIAS
6dB
I2C BUS
sPACKAGE OUTLINE
NJW1320FP1
Y OUT1
Y OUT2
Y OUT3
Pb OUT1
Pb OUT2
Pb OUT3
Pr OUT1
Pr OUT2
Pr OUT3
ADDRESS
SDA
SCL
AUX 0
AUX 1
AUX 2
AUX 3
DGND
Ver.8
-1-
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NJW1320
s I2C BUS BLOCK CHARACTERISTICS (SDA,SCL)
I2C BUS Load Conditions
STANDARD MODE: Pull up resistance 4kΩ (Connected to +5V), Load capacitance 200pF (Connected to GND)
PARAMETER
SYMBOL MIN TYP MAX UNIT
Low Level Input Voltage
High Level Input Voltage
LOW level Output Voltage (3mA at SDA pin)
Output Fall Time From VIHmin to VILmax
with a Bus Capacitancefrom 10pF to 400pF
Input Current each I/O pin with an Input Voltage
between 0.1 and 0.9VDDmax
Capacitance for each I/O pin
SCL Clock Frequency
Data Transfer Start Minimum Waiting Time
Low Level Clock Pulse Width
High Level Clock Pulse Width
Minimum Start Preparation Waiting Time
Minimum Data Hold Time
Minimum Data Preparation Time
Rise Time
Fall Time
Minimum Stop Preparation Waiting Time
Data Change Minimum Waiting Time
Capacitive load for each bus line
Noise Margin at the Low Level
Noise Margin at the High Level
VIL
VIH
VOL
tof
Ii
Ci
fSCL
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
tf
tSU:STO
tBUF
Cb
VnL
VnH
0.0 - 1.5
2.7 - 5.5
0 - 0.4
V
V
V
- - 250 ns
-10 - 10 µA
- - 10 pF
- - 100 kHz
4.0 - - µs
4.7 - - µs
4.0 - - µs
4.7 - - µs
0 - - µs
250 - - ns
- - 1000 ns
- - 300 ns
4.0 - - µs
4.7 - - µs
- - 400 pF
0.5 -
-
V
1- -
V
Cb ; total capacitance of one bus line in pF.
SDA
tf tr
SCL
tHD:ST A
S
tLOW
tSU:DAT
tf
tHD:S T A
tHD:DAT
tHIGH
tS U:S T A
Sr
tSP tr
tBUF
tSU:S T O
P
S
-4-
4페이지 www.DataSheet4U.com
s DEFINITION OF I2C REGISTER
♦I2C BUS FORMAT
MSB
LSB MSB
S Slave Address A
1bit 8bit
S: Starting Term
A: Acknowledge Bit
P: Ending Term
1bit
Data
8bit
♦SLAVE ADDRESS
R/W: Set the Write Mode or Read Mode.
ADR : Set the Slave Address by “ADR” terminal.
LSB MSB
A
1bit
Data
8bit
Slave Address
MSB
10000
x R/W = 0 : Write Mode, ADR = 0/1
10010
10010
x R/W = 1 : Read Mode, ADR = 0/1
10010
10010
0
1
1
1
1
ADR
0
1
0
1
LSB
R/W
0
0
1
1
Hex
-
-
-
94(h)
96(h)
-
95(h)
97(h)
♦CONTROL REGISTER TABLE
< Write Mode >
No.
Data1
Data2
Data3
D7 D6
PS2 PS3
OUT3
AUX0
BIT
D5 D4
OUT1
AUX1
D3 D2
✴
AUX2
< Read Mode >
No.
Data
D7 D6
PORT0
BIT
D5 D4 D3 D2
PORT1
PORT2
♦CONTROL REGISTER DEFAULT VALUE
Control register default value is all “0”.
No.
D7 D6 D5
Data1
0
0
0
Data2
0
0
0
Data3
0
0
0
BIT
D4 D3
00
00
00
D2
0
0
0
NJW1320
LSB
A
P
1bit 1bit
D1
OUT2
D0
AUX3
✴ : Don’t Care
D1 D0
PORT3
D1 D0
00
00
00
-7-
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
NJW1320 | Video Switch / QFP48-P1 | JRC |
NJW1321 | Video Switch / QFP48-P1 | JRC |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |