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PDF AD7357 Data sheet ( Hoja de datos )
| Número de pieza | AD7357 | |
| Descripción | SAR ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Preliminary Technical Data
Differential Input, Dual, Simultaneous
Sampling, 4.2 MSPS, 14-Bit, SAR ADC
AD7357
FEATURES
Dual 14-bit SAR ADC
Simultaneous sampling
Throughput rate: 4.2 MSPS per channel
Specified for VDD of 2.5 V
Power dissipation: 35 mW at 4.2 MSPS
On-chip reference: 2.048 V ± 0.25%, 6 ppm/°C
Dual conversion with read
High speed serial interface
SPI-/QSPI-/MICROWIRE-/DSP-compatible
−40°C to +125°C operation
Shutdown mode: 10 µA maximum
16-lead TSSOP package
VINA+
VINA–
REFA
FUNCTIONAL BLOCK DIAGRAM
VDD
VDRIVE
AD7357
T/H
14-BIT
SUCCESSIVE
APPROXIMATION
ADC
SDATAA
BUF
REF
BUF
CONTROL
LOGIC
SCLK
CS
REFB
VINB+
VINB–
14-BIT
SUCCESSIVE
T/H
APPROXIMATION
ADC
SDATAB
GENERAL DESCRIPTION
The AD73571 is a dual, 14-bit, high speed, low power, successive
approximation analog-to-digital converter (ADC) that operates
from a single 2.5 V power supply and features throughput rates up
to 4.2 MSPS. The part contains two ADCs, each preceded by a low
noise, wide bandwidth track-and-hold circuit that can handle input
frequencies in excess of 110 MHz.
The conversion process and data acquisition use standard control
inputs allowing for easy interfacing to microprocessors or DSPs.
The input signal is sampled on the falling edge of CS; conversion is
also initiated at this point. The conversion time is determined by
the SCLK frequency.
The AD7357 uses advanced design techniques to achieve very low
power dissipation at high throughput rates. With 2.5 V supply and
a 4.2 MSPS throughput rate, the part consumes 14 mA typically.
The part also offers flexible power/throughput rate management
options.
The analog input range for the part is the differential common
mode +/- VREF/2. The AD7357 has an on-chip 2.048 V reference
that can be overdriven when an external reference is preferred.
The AD7357 is available in a 16-lead thin shrink small outline
package (TSSOP).
AGND
AGND
REFGND
Figure 1.
DGND
PRODUCT HIGHLIGHTS
1. Two Complete ADC Functions.
These functions allow simultaneous sampling and
conversion of two channels. The conversion result of both
channels is simultaneously available on separate data lines
or in succession on one data line if only one serial port is
available.
2. High Throughput with Low Power Consumption.
The AD7357 offers a 4.2 MSPS throughput rate with 35
mW power consumption.
3. Simultaneous Sampling.
The part features two standard successive approximation
ADCs with accurate control of the sampling instant via a
CS input and once off conversion control.
Table 1. Related Devices
Generic Resolution Throughput
AD7356 12-bit
5 MSPS
AD7352 12-bit
3 MSPS
AD7266 12-bit
2 MSPS
AD7866 12-bit
1 MSPS
AD7366 12-bit
1 MSPS
AD7367 14-bit
1 MSPS
Analog Input
Differential
Differential
Differential/Single-Ended
Single-Ended
Single-Ended Bipolar
Single-Ended Bipolar
1 Protected by U.S. Patent No. 6,681,332.
Rev. PrF
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
1 page  
www.DParteaSlihmeeitn4aU.rcyomTechnical Data
AD7357
TIMING SPECIFICATIONS
VDD = 2.5 V ± 10%, VDRIVE = 2.25 V to 3.6 V, internal reference = 2.048 V, TA = TMAX to TMIN1, unless otherwise noted.
Table 3.
Parameter
fSCLK
tCONVERT
tQUIET
t2
t32
t42, 3
t5
t6
t72
t8
t9
t102
Latency
Limit at TMIN, TMAX
50
80
t2 + 15 × tSCLK
5
5
6
Unit
kHz min
MHz max
ns max
ns min
ns min
ns max
12.5 ns max
11 ns max
9.5 ns max
9 ns max
5 ns min
5 ns min
3.5 ns min
9.5 ns max
5 ns min
4.5 ns min
9.5 ns max
1 conversion latency
Description
tSCLK = 1/fSCLK
Minimum time between end of serial read and next falling edge of CS
CS to SCLK setup time
Delay from CS until SDATAA and SDATAB are three-state disabled
Data access time after SCLK falling edge
1.8 V ≤ VDRIVE < 2.25 V
2.25 V ≤ VDRIVE < 2.75 V
2.75 V ≤ VDRIVE < 3.3 V
3.3 V ≤ VDRIVE ≤ 3.6 V
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
CS rising edge to SDATAA, SDATAB, high impedance
CS rising edge to falling edge pulse width
SCLK falling edge to SDATAA, SDATAB, high impedance
SCLK falling edge to SDATAA, SDATAB, high impedance
1 Temperature ranges are as follows: Y grade: −40°C to +125°C, B grade: −40°C to +85°C.
2 Specified with a load capacitance of 10 pF on SDATAA and SDATAB.
3 The time required for the output to cross 0.4 V or 2.4 V.
Rev. PrF | Page 5 of 20
5 Page 
www.DParteaSlihmeeitn4aU.rcyomTechnical Data
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to zero. For
example, the second-order terms include (fa + fb) and (fa − fb),
while the third-order terms include (2fa + fb), (2fa − fb), (fa +
2fb), and (fa − 2fb).
The AD7357 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, while the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification, where it is the ratio of the rms
AD7357
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in decibels.
Thermal Hysteresis
Thermal hysteresis is defined as the absolute maximum change
of reference output voltage after the device is cycled through
temperature from either
T_HYS+ = 25°C to TMAX to 25°C
T_HYS– = 25°C to TMIN to 25°C
It is expressed in ppm using the following equation:
VHYS ( ppm) =
VREF (25°C) − VREF (T _ HYS)
VREF (25°C)
× 106
where:
VREF(25°C) is VREF at 25°C
VREF(T_HYS) is the maximum change of VREF at T_HYS+ or
T_HYS–.
Rev. PrF | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD7357.PDF ] | |
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