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AD7190 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD7190은 전자 산업 및 응용 분야에서
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부품번호 AD7190 기능
기능 4.8 kHz Ultra-Low Noise 24-Bit Sigma-Delta ADC
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AD7190 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Preliminary Technical Data
FEATURES
RMS Noise: 7 nV @ 4.7 Hz (gain = 128)
16.5 noise free bits @ 2.4 kHz (gain = 128)
Up to 23 noise free bits (gain = 1)
Offset drift: 5 nV/°C
Gain drift: 2 ppm/°C
Specified drift over time
Programmable gain (1 – 128)
Update rate: 4.7 Hz to 4.8 kHz
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection
Four general purpose digital outputs
Power supply: 3 V to 5.25 V
Current: 6 mA
Temperature range: –40°C to +105°C
INTERFACE
3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Weigh scales
Strain gauge transducers
Pressure measurement
Temperature measurement
Chromatography
4.8 kHz Ultra-Low Noise 24-Bit
Sigma-Delta ADC with PGA
AD7190
PLC/DCS Analog Input Modules
Data Acquisition
Medical and Scientific instrumentation
GENERAL DESCRIPTION
The AD7190 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise, 24-
bit ∑-∆ ADC. The on-chip low noise gain stage means that
signals of small amplitude can be interfaced directly to the
ADC.
The device can be configured to have two differential inputs or
four pseudo-differential inputs. The device can be operated
with either the internal clock or an external clock. The output
data rate from the part can be varied from 4.7 Hz to 4.8 kHz.
The device can be operated with a sinc3 or a sinc4 digital filter.
At the lower update rates, the sinc3 is useful to optimize the
settling time. The benefit of the sinc4 at low update rates is the
superior 50 Hz/60 Hz rejection. At the higher update rates, the
sinc4 filter gives best noise performance. For applications that
require all conversions to be settled, the AD7190 includes a
zero-latency feature.
The part operates with a power supply from 3 V to 5.25 V. It
consumes a current of 6 mA. It is housed in a 24-lead TSSOP
package.
AVDD
FUNCTIONAL BLOCK DIAGRAM
AGND
DVDD DGND
REFIN1(+) REFIN1(-)
AIN1
AIN2
AIN3
AIN4
AINCOM
BPDSW
AGND
AD7190
AVDD
MUX
PGA
SIGMA DELTA
ADC
AGND
TEMP
SENSOR
CLOCK
CIRCUITRY
REFERENCE
DETECT
SERIAL
INTERFACE
AND CONTROL
LOGIC
DOUT/RDY
DIN
SCLK
CS
SYNC
P3
P2
MCLK1
MCLK2
Figure 1.
P0/REFIN2(-) P1/REFIN2(+)
Rev.PrD
7/08
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2008 Analog Devices, Inc. All rights reserved.




AD7190 pdf, 반도체, 판매, 대치품
wwAwD.7D1at9a0Sheet4U.com
Preliminary Technical Data
Parameter1
VOL, Output Low Voltage2
Floating-State Leakage Current
Floating-State Output Capacitance
Data Output Coding
SYSTEM CALIBRATION2
Full-Scale Calibration Limit
Zero-Scale Calibration Limit
Input Span
POWER REQUIREMENTS7
Power Supply Voltage
AVDD AGND
DVDD DGND
Power Supply Currents
AIDD Current
DIDD Current
IDD (Power-Down Mode)
AD7190B
0.4
±10
10
Offset binary
1.05 × FS
1.05 × FS
0.8 × FS
2.1 × FS
3/5.25
2.7/5.25
TBD
TBD
TBD
TBD
TBD
TBD
1
1
Unit
V max
µA max
pF typ
V max
V min
V min
V max
V min/max
V min/max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
µA max
Test Conditions/Comments
DVDD = 5 V, ISINK = 1.6 mA
Gain = 1, Buffer off
Gain = 8, Buffer off
Gain = 8, Buffer on
Gain = 16 – 128, Buffer off
Gain = 16 – 128, Buffer on
DVDD = 3 V
DVDD = 5 V
1 Temperature range: −40°C to +105°C.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Following a calibration, this error will be in the order of the noise for the programmed gain and update rate selected.
4 Recalibration at any temperature will remove these errors.
5 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 5 V, gain = 1, TA = 25°C).
6 REJ60 is a bit in the Mode Register. When the update rate is set to 50 Hz, setting REJ60 to ‘1’ places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection.
7 Digital inputs equal to DVDD or GND.
Rev.PrD 7/08 | Page 4

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AD7190 전자부품, 판매, 대치품
www.DParteaSlihmeeint4aUr.cyomTechnical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
AVDD to GND
DVDD to GND
Analog Input Voltage to GND
Reference Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
AIN/Digital Input Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
TSSOP
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
0.3 V to +6.5 V
0.3 V to +6.5 V
0.3 V to AVDD + 0.3 V
0.3 V to AVDD + 0.3 V
0.3 V to DVDD + 0.3 V
0.3 V to DVDD + 0.3 V
10 mA
40°C to +105°C
65°C to +150°C
150°C
97.9°C/W
14°C/W
215°C
220°C
AD7190
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev.PrD 7/08 | Page 7

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