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LF2242 데이터시트 PDF




LOGIC Devices Incorporated에서 제조한 전자 부품 LF2242은 전자 산업 및 응용 분야에서
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부품번호 LF2242 기능
기능 12/16-bit Half-Band Interpolating/ Decimating Digital Filter
제조업체 LOGIC Devices Incorporated
로고 LOGIC Devices Incorporated 로고


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LF2242 데이터시트, 핀배열, 회로
DEVICES INCORPORATED
DEVICES INCORPORATED
LF2242
LF224212/16-bit Half-Band Interpolating/
12/16-bit Half-BaDnecdimInattinegrpDoigliatatilnFgilt/er
Decimating Digital Filter
FEATURES
DESCRIPTION
u 40 MHz Clock Rate
u Passband (0 to 0.22fS)
Ripple: ±0.02 dB
u Stopband (0.28fS to 0.5fS)
Rejection: 59.4 dB
u User-Selectable 2:1 Decimation or
1:2 Interpolation
u 12-bit Two’s Complement Input
and 16-bit Output with
User-Selectable Rounding, 8- to
16-Bits
u User-Selectable Two’s Complement
or Inverted Offset Binary Output
Formats
u Three-State Outputs
u Replaces TRW/ Raytheon/
Fairchild TMC2242
u Package Styles Available:
• 44-pin PLCC, J-Lead
• 44-pin PQFP
The LF2242 is a linear-phase, half-
band (low pass) interpolating/
decimating digital filter that, unlike
intricate analog filters, requires no
tuning. The LF2242 can also signifi-
cantly reduce the complexity of
traditional analog anti-aliasing pre-
filters without compromising the
signal bandwidth or attenuation. This
can be achieved by using the LF2242
as a decimating post-filter with an
A/D converter and by sampling the
signal at twice the rate needed.
Likewise, by using the LF2242 as an
interpolating pre-filter with a D/A
converter, the corresponding analog
reconstruction post-filter circuitry can
be simplified.
The coefficients of the LF2242 are
fixed, and the only user programming
required is the selection of the mode
(interpolate, decimate, or pass-
through) and rounding. The asyn-
chronous three-state output enable
control simplifies interfacing to a bus.
Data can be input into the LF2242 at a
rate of up to 40 million samples per
second. Within the 40 MHz I/O limit,
the output sample rate can be one-
half, equal to, or two times the input
sample rate. Once data is clocked in,
the 55-value output response begins
after 7 clock cycles and ends after 61
clock cycles. The pipeline latency
from the input of an impulse response
to its corresponding output peak is 34
clock cycles.
The output data may be in either
two’s complement format or inverted
offset binary format. To avoid
truncation errors, the output data is
always internally rounded before it is
latched into the output register.
Rounding is user-selectable, and the
output data can be rounded from 16
bit values down to 8 bit values.
DC gain of the LF2242 is 1.0015
(0.0126 dB) in pass-through and
decimate modes and 0.5007 (–3.004
dB) in interpolate mode. Passband
ripple does not exceed ±0.02 dB from
0 to 0.22fS with stopband attenuation
greater than 59.4 dB from 0.28fS to
0.5fS (Nyquist frequency). The
response of the filter is –6 dB at 0.25fS.
Full compliance with CCIR Recom-
mendation 601 (–12 dB at 0.25fS) can
be achieved by cascading two devices
serially.
LF2242 BLOCK DIAGRAM
TCO RND2–0
3
12
SI11–0
INTERPOLATION 12
CIRCUIT
3
55-TAP
FIR
FILTER
3
ROUND
AND LIMIT
CIRCUIT
16
DECIMATION
CIRCUIT
3
16
SO15–0
CLK TO ALL REGISTERS
INT DEC SYNC
1
OE
Video Imaging Products
08/16/2000–LDS.2242-K




LF2242 pdf, 반도체, 판매, 대치품
DEVICES INCORPORATED
LF2242
12/16-bit Half-Band Interpolating/
Decimating Digital Filter
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ............................................................................... –0.5 V to VCC + 0.5 V
Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Active Operation, Commercial
Active Operation, Industrial
Temperature Range (Ambient)
0°C to +70°C
-40°C to +85°C
Supply Voltage
4.75 V VCC 5.25 V
4.75 V VCC 5.25 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol Parameter
Test Condition
VOH Output High Voltage
VCC = Min., IOH = –2.0 mA
VOL Output Low Voltage
VCC = Min., IOL = 4.0 mA
VIH Input High Voltage
VIL Input Low Voltage
(Note 3)
IIX Input Current
Ground VIN VCC (Note 12)
IOZ Output Leakage Current (Note 12)
ICC1 VCC Current, Dynamic
(Notes 5, 6)
ICC2 VCC Current, Quiescent (Note 7)
CIN Input Capacitance
TA = 25°C, f = 1 MHz
COUT Output Capacitance
TA = 25°C, f = 1 MHz
Min Typ Max Unit
2.4 V
0.4 V
2.0 VCC V
0.0 0.8 V
±10 µA
±10 µA
80 mA
10 mA
10 pF
10 pF
Video Imaging Products
4 08/16/2000–LDS.2242-K

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LF2242 전자부품, 판매, 대치품
DEVICES INCORPORATED
LF2242
12/16-bit Half-Band Interpolating/
Decimating Digital Filter
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.
2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations of static charge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. Thisdeviceprovideshardclampingof
transient undershoot and overshoot. In-
put levels below ground or above VCC
will be clamped beginning at –0.6 V and
VCC + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of –0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.
4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.
5. Supply current for a given applica-
tion can be accurately approximated by:
where
NCV2 F
4
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 20 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of IOH and IOL respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 µF ceramic capacitor should be
installed between VCC and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device VCC
and the tester common, and device
ground and tester common.
b. Ground and VCC supply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, VTH, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
CL
IOL
VTH
IOH
FIGURE B. THRESHOLD LEVELS
tENA
tDIS
OE 1.5 V
1.5 V
Z0
1.5 V
VOL* 0.2 V
3.5V Vth
0Z
Z1
1.5 V
VOH* 0.2 V
1Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
Video Imaging Products
7 08/16/2000–LDS.2242-K

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