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PDF F25L008A Data sheet ( Hoja de datos )
| Número de pieza | F25L008A | |
| Descripción | 8Mbit (1Mx8) 3V Only Serial Flash Memory | |
| Fabricantes | Elite Semiconductor | |
| Logotipo |  |
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FEATURES
y Single supply voltage 2.7~3.6V
y Speed
- Read max frequency : 33MHz
- Fast Read max frequency : 50MHz; 100MHz
y Low power consumption
- typical active current
- 15 μ A typical standby current
y Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
y Program
- Byte program time 7 μ s(typical)
y Erase
- Chip erase time 8s(typical)
block erase time 1sec (typical)
F25L008A
8Mbit (1Mx8)
3V Only Serial Flash Memory
- Sector erase time 60ms (typical),
y Auto Address Increment (AAI) WORD Programming
- Decrease total chip programming time over
Byte-Program operations
y SPI Serial Interface
- SPI Compatible : Mode 0 and Mode3
y End of program or erase detection
y Write Protect ( WP )
y Hold Pin ( HOLD )
y Package available
- 8-pin SOIC 200-mil
ORDERING INFORMATION
Part No.
Speed
Package
COMMENTS
F25L008A –50PAG 50MHz 8 lead SOIC 200mil
Pb-free
F25L008A –100PAG 100MHz 8 lead SOIC 200mil
Pb-free
F25L008A –50DG 50MHz 8 lead PDIP 300mil
Pb-free
F25L008A –100DG 100MHz 8 lead PDIP 300mil
Pb-free
GENERAL DESCRIPTION
The F25L008A is a 8Megablt, 3V only CMOS Serial Flash
memory device organized as 1M bytes of 8 bits. This device is
packaged in 8-lead SOIC 200mil. ESMT’s memory devices
reliably store memory data even after 100,000 program and
erase cycles.
The F25L008A features a sector erase architecture. The device
memory array is divided into 256 uniform sectors with 4K byte
each ; 16 uniform blocks with 64K byte each. Sectors can be
erased individually without affecting the data in other sectors.
Blocks can be erased individually without affecting the data in
other blocks. Whole chip erase capabilities provide the flexibility
to revise the data in the device.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.4 1/31
1 page  
ESMTwww.DataSheet4U.com
47
2:
32
31
1:
16
15
0:
0
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
02F000H – 02FFFFH
:
020000H – 020FFFH
01F000H – 01FFFFH
:
010000H – 010FFFH
00F000H – 00FFFFH
:
000000H – 000FFFH
00 1 0
00 0 1
00 0 0
F25L008A
Table2 : F25L008A Block Protection Table
TOP
Protection Level
0
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
All Blocks
All Blocks
All Blocks
Status Register Bit
BP2 BP1 BP0
000
001
010
011
100
101
110
111
Protected Memory Area
Block Range
Address Range
None
None
Block 15
F0000H – FFFFFH
Block 14~15
E0000H – FFFFFH
Block 12~15
C0000H – FFFFFH
Block 8~15
80000H – FFFFFH
Block 0~15
00000H – FFFFFH
Block 0~15
00000H – FFFFFH
Block 0~15
00000H – FFFFFH
BOTTOM
Protection Level
0
Bottom 1/16
Bottom 1/8
Bottom 1/4
Bottom 1/2
All Blocks
All Blocks
All Blocks
Status Register Bit
BP2 BP1 BP0
000
001
010
011
100
101
110
111
Protected Memory Area
Block Range
Address Range
None
None
Block 0
00000H – 0FFFFH
Block 0~1
00000H – 1FFFFH
Block 0~3
00000H – 3FFFFH
Block 0~7
00000H – 7FFFFH
Block 0~15
00000H – FFFFFH
Block 0~15
00000H – FFFFFH
Block 0~15
00000H – FFFFFH
Block Protection (BP2, BP1, BP0)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table2 to be software protected
against any memory Write (Program or Erase) operations. The
Write-Status-Register (WRSR) instruction is used to program the
BP2, P1, BP0 bits as long as WP is high or the
Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be
executed if Block-Protection bits are all 0. After power-up, BP2,
BP1 and BP0 are set to1.
Block Protection Lock-Down (BPL)
WP pin driven low (VIL), enables the Block-Protection
-Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP2, BP1, and BP0 bits. When the
WP pin is driven high (VIH), the BPL bit has no effect and its
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.4 5/31
5 Page 
ESMTwww.DataSheet4U.com
F25L008A
Fast-Read (50 MHz ; 100 MHz)
The High-Speed-Read instruction supporting up to 100 MHz is
initiated by executing an 8-bit command, 0BH, followed by
address bits [A23-A0] and a dummy byte. CE must remain active
low for the duration of the High-Speed-Read cycle. See Figure 3
for the High-Speed-Read sequence.
Following a dummy byte (8 clocks input dummy cycle), the
High-Speed-Read instruction outputs the data starting from the
specified address location. The data output stream is continuous
through all addresses until terminated by a low to high transition
on CE . The internal address pointer will automatically increment
until the highest memory address is reached. Once the highest
memory address is reached, the address pointer will
automatically increment to the beginning (wrap-around) of the
address space, i.e. for 8Mbit density, once the data from address
location FFFFFH has been read, the next output will be from
address location 000000H.
CE
MODE3
SCK MODE0
0 12 3 45 67 8
15 16 23 24
31 32 39 40 47 48 55 56 63 64 71 72
80
SI
0B
ADD.
ADD.
A DD.
MSB
MSB
SO HIGH IMPENANCE
Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH)
X
N
D OU T
MSB
N+1
DOUT
N+2
DOUT
N+3
D OU T
N+4
D OU T
Figure 3 : HIGH-SPEED-READ SEQUENCE
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision: 1.4 11/31
11 Page | ||
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| PDF Descargar | [ Datasheet F25L008A.PDF ] | |
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