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LF2272QC20 데이터시트 PDF




LOGIC Devices Incorporated에서 제조한 전자 부품 LF2272QC20은 전자 산업 및 응용 분야에서
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부품번호 LF2272QC20 기능
기능 Colorspace Converter/Corrector (3 x 12-bits)
제조업체 LOGIC Devices Incorporated
로고 LOGIC Devices Incorporated 로고


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LF2272QC20 데이터시트, 핀배열, 회로
DEVICES INCORPORATED
DEVICES INCORPORATED
LF2272
ColorspaLceFC2on2v7er2ter/
ColorspCoarcreectCoro(n3vxe1r2t-ebrit/s)
Corrector (3 x 12-bits)
FEATURES
DESCRIPTION
u 50 MHz Data and Computation
Rate
u Full Precision Internal Calculations
with Output Rounding
u On-board 10-bit Coefficient Storage
u Overflow Capability in Low
Resolution Applications
u Two’s Complement Input and
Output Data Format
u 3 Simultaneous 12-bit Channels
(64 Giga Colors)
u Applications:
• Component Color Standards
Translations (RGB, YIQ, YUV)
• Color-Temperature Conversion
• Image Capturing and Manipulation
• Composite Color Encoding/
Decoding
• Three-Dimensional Perspective
Translation
u Replaces TRW/Raytheon/Fairchild
TMC2272
u 120-pin PQFP
The LF2272 is a high-speed digital
colorspace converter/corrector
consisting of three simultaneous 12-bit
input and output channels for func-
tionality up to 64 Giga (236) colors.
Some of the applications the LF2272
can be used for include phosphor
colorimetry correction, image captur-
ing and manipulation, composite color
encoding/decoding, color matching,
and composite color standards
conversion/transcoding.
The 3 x 3 matrix multiplier (triple dot
product) allows users to easily per-
form three-dimensional perspective
translations or video format conver-
sions at real-time video rates. By
using the LF2272, conversions can be
made from the RGB (color compo-
nent) format to the YIQ (quadrature
encoded chrominance) or YUV (color
difference) formats and vice versa
(YIQ or YUV to RGB). Differing signal
formats in each stage of a system can
be disregarded. For example, using
an LF2272 at each format interface
allows each stage of a system to
operate on the data while in the
appropriate format.
All inputs and outputs, as well as all
control lines, are registered on the
rising edge of clock. The LF2272
operates at clock rates up to 50 MHz
over the full commercial temperature
and supply voltage ranges. A nar-
rower data path can be used to allow
the LF2272 to work with many
different imaging applications.
DETAILS OF OPERATION
All three input ports (A, B, C) and all
three output ports (X, Y, Z) are
utilized to implement a 3 x 3 matrix
multiplication (triple dot product).
Each truncated 12-bit output is the
sum of all three input words multi-
plied by the appropriate coefficients
(Table 1). The pipeline latency is five
clock cycles. Therefore, the sum of
LF2272 BLOCK DIAGRAM
CLK
CWEL1-0
2
{DATA
INPUTS
A11-0
B11-0
C11-0
{COEFFICIENT
INPUTS
KA9-0
KB9-0
KC9-0
12
12
12
10
10
10
9-MULTIPLIER
ARRAY
12 X11-0
12
Y11-0
DATA
OUTPUTS
12 Z11-0
Video Imaging Products
1 08/16/2000–LDS.2272-I




LF2272QC20 pdf, 반도체, 판매, 대치품
DEVICES INCORPORATED
FIGURE 2. DETAILED FUNCTIONAL DIAGRAM
12
A
10
KA
KA1
LF2272
Colorspace Converter/
Corrector (3 x 12-bits)
KA2
KA3
12
B
10
KB
21 21 21
KB1
KB2
KB3
12
C
10
KC
21
KC1
21
KC2
21
KC3
2
CWEL
21 21 21
12 (MSB)
X
12 (MSB)
Y
12 (MSB)
Z
Video Imaging Products
4 08/16/2000–LDS.2272-I

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LF2272QC20 전자부품, 판매, 대치품
DEVICES INCORPORATED
LF2272
Colorspace Converter/
Corrector (3 x 12-bits)
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.
2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations of static charge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. Thisdeviceprovideshardclampingof
transient undershoot and overshoot. In-
put levels below ground or above VCC
will be clamped beginning at –0.6 V and
VCC + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of –0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.
4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.
5. Supply current for a given applica-
tion can be accurately approximated by:
where
NCV2 F
4
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 20 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of IOH and IOL respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 µF ceramic capacitor should be
installed between VCC and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device VCC
and the tester common, and device
ground and tester common.
b. Ground and VCC supply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, VTH, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
CL
IOL
VTH
IOH
FIGURE B. THRESHOLD LEVELS
tENA
tDIS
OE 1.5 V
1.5 V
Z0
1.5 V
VOL* 0.2 V
3.0V Vth
0Z
Z1
1.5 V
VOH* 0.2 V
1Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
Video Imaging Products
7 08/16/2000–LDS.2272-I

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