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PDF ATtiny87 Data sheet ( Hoja de datos )
| Número de pieza | ATtiny87 | |
| Descripción | 8-bit Atmel Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High Performance, Low Power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 123 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• Non-volatile Program and Data Memories
– 8K/16K Bytes of In-System Programmable Flash Program Memory
• Endurance: 10,000 Write/Erase Cycles
– 512 Bytes of In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 512 Bytes of Internal SRAM
– Data retention: 20 Years at 85°C / 100 Years at 25°C
– In-System Programmable via SPI Port
– Low size LIN/UART Software In-System Programmable
– Programming Lock for Software Security
• Peripheral Features
– LIN 2.1 and 1.3 Controller or 8-bit UART
– One 8-bit Asynchronous Timer/Counter with Prescaler
• Output Compare or 8-bit PWM Channel
– One 16-bit Synchronous Timer/Counter with Prescaler
• External Event Counter
• 2 Output Compare Units or PWM Channels each Driving up to 4 Output Pins
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– 10-bit ADC
• 11 Single Ended Channels
• 8 Differential ADC Channel Pairs with Programmable Gain (8x or 20x)
– On-chip Analog Comparator with Selectable Voltage Reference
– 100 µA ±10% Current Source for LIN Node Identification
– On-chip Temperature Sensor
– Programmable Watchdog Timer with Separate On-chip Oscillator
• Special Microcontroller Features
– Software Controlled Clock Switching for Power Control, EMC Reduction
– debugWIRE On-chip Debug System
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Power-on Reset and Programmable Brown-out Detection
– Internal 8MHz Calibrated Oscillator
– 4-16 MHz and 32 KHz Crystal/Ceramic Resonator Oscillators
• I/O and Packages
– 16 Programmable I/O Lines
– 20-pin SOIC, 32-pad VQFN and 20-pin TSSOP
• Operating Voltage:
– 1.8 – 5.5V for ATtiny87/167
• Speed Grade:
– 0 – 4 MHz @ 1.8 – 5.5V
– 0 – 8 MHz @ 2.7 – 5.5V
– 0 – 16 MHz @ 4.5 – 5.5V
• Industrial Temperature Range
8-bit Atmel
Microcontroller
with 8K/16K
Bytes In-System
Programmable
Flash and LIN
Controller
ATtiny87
ATtiny167
Rev. 8265D–AVR–01/2014
1 page  
ATtiny87/167
1.5 Pin Description
1.5.1 VCC
Supply voltage.
1.5.2 GND
Ground.
1.5.3 AVCC
Analog supply voltage.
1.5.4 AGND
Analog ground.
1.5.5
Port A (PA7:PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the ATtiny87/167 as listed on Sec-
tion 9.3.3 “Alternate Functions of Port A” on page 76.
1.5.6
Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny87/167 as listed on Sec-
tion 9.3.4 “Alternate Functions of Port B” on page 81.
8265D–AVR–01/2014
5
5 Page 
ATtiny87/167
Figure 2-3. The X-, Y-, and Z-registers
X-register
Y-register
Z-register
15
7
R27 (0x1B)
15
7
R29 (0x1D)
15
7
R31 (0x1F)
XH
YH
ZH
0
07
R26 (0x1A)
07
R28 (0x1C)
7
R30 (0x1E)
XL
YL
ZL
0
0
0
0
0
0
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
2.5 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present
2.5.1 SPH and SPL – Stack Pointer Register
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
15
SP15
SP7
7
R/W
R/W
14
SP14
SP6
6
R/W
R/W
13 12 11 10
SP13
SP12
SP11
SP10
SP5 SP4 SP3 SP2
5432
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ISRAM end (See Table 3-1 on page 15)
9
SP9
SP1
1
R/W
R/W
8
SP8
SP0
0
R/W
R/W
SPH
SPL
8265D–AVR–01/2014
11
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