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PDF ADP3121 Data sheet ( Hoja de datos )
| Número de pieza | ADP3121 | |
| Descripción | 12V MOSFET Driver | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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ADP3121
Dual Bootstrapped, 12 V
MOSFET Driver with Output
Disable
The ADP3121 is a dual, high voltage MOSFET driver optimized for
driving two N−channel MOSFETs, the two switches in a non−isolated
synchronous buck power converter. Each driver is capable of driving a
3000 pF load with a 20 ns propagation delay and a 15 ns transition
time.
One of the drivers can be bootstrapped and is designed to handle the
high voltage slew rate associated with floating high−side gate drivers.
The ADP3121 includes overlapping drive protection to prevent
shoot−through current in the external MOSFETs.
The OD pin shuts off both the high−side and the low−side
MOSFETs to prevent rapid output capacitor discharge during system
shutdown.
The ADP3121 is specified over the commercial temperature range
of 0°C to 85°C and is available in 8−lead SOIC_N and 8−lead LFCSP
packages.
Features
• All−In−One Synchronous Buck Driver
• Bootstrapped High−Side Drive
• One PWM Signal Generates Both Drives
• Anticross Conduction Protection Circuitry
• Overvoltage Protection
• OD for Disabling the Driver Outputs
• Meets CPU VR Requirement when Used with Flex−Modet
Controller
• These are Pb−Free Devices
Typical Applications
• Multiphase Desktop CPU Supplies
• Single Supply Synchronous Buck Converters
http://onsemi.com
MARKING
DIAGRAMS
8 SO−8
1
D SUFFIX
CASE 751−07
8
P3121
ALYW G
G
P3121A = Device Code
1
AL = Assembly Location
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
8
1
LFCSP8
MN SUFFIX
CASE 932AF
L7Q
#YWW
L7Q = Device Code
# = Pb−Free Package
Y = Year
WW = Work Week
PIN ASSIGNMENT
BST
IN
OD
VCC
DRVH
SWN
PGND
DRVL
ORDERING INFORMATION
Device
Package
Shipping†
ADP3121JRZ−RL SOIC_N 2500/Tape & Reel
(Pb−Free)
ADP3121JCPZ−RL LFCSP_VD 5000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2010
February, 2010 − Rev. 1
1
Publication Order Number:
ADP3121/D
1 page  
ADP3121
Theory of Operation
The ADP3121 is optimized for driving two N−channel
MOSFETs in a synchronous buck converter topology. A
single PWM input signal is all that is required to properly
drive the high side and the low−side MOSFETs. Each driver
is capable of driving a 3 nF load at speeds up to 500 kHz. A
functional block diagram of ADP3121 is shown in Figure 1.
Low−Side Driver
The low−side driver is designed to drive a ground
referenced N−channel MOSFET. The bias to the low−side
driver is internally connected to the VCC supply and PGND.
When the driver is enabled, the driver output is 180° out
of phase with the PWM input. When the ADP3121 is
disabled, the low−side gate is held low.
High−Side Driver
The high−side driver is designed to drive a floating
N−channel MOSFET. The bias voltage for the high−side
driver is developed by an external bootstrap supply circuit
that is connected between the BST and SW pins.
The bootstrap circuit comprises Diode D1 and Bootstrap
Capacitor CBST1. CBST2 and RBST are included to reduce the
high−side gate drive voltage and to limit the switch node
slew rate (called a Boot−Snap circuit). When the ADP3121
starts up, the SW pin is at ground, so the bootstrap capacitor
charges up to VCC through D1. When the PWM input goes
high, the high−side driver begins to turn on the high−side
MOSFET, Q1, by pulling charge out of CBST1 and CBST2. As
Q1 turns on, the SW pin rises up to VIN and forces the BST
pin to VIN + VC (BST). This holds Q1 on because enough
gate−to−source voltage is provided. To complete the cycle,
Q1 is switched off by pulling the gate down to the voltage at
the SW pin. When the low−side MOSFET, Q2, turns on, the
SW pin is pulled to ground. This allows the bootstrap
capacitor to charge up to VCC again.
The output of the high−side driver is in phase with the
PWM input. When the driver is disabled, the high−side gate
is held low.
Overlap Protection Circuit
The overlap protection circuit prevents both of the main
power switches, Q1 and Q2, from being on at the same time.
This is done to prevent shoot−through currents from flowing
through both power switches and the associated losses that
can occur during their on/off transitions. The overlap
protection circuit accomplishes this by adaptively
controlling the delay from the Q1 turn−off to the Q2 turn−on,
and by internally setting the delay from the Q2 turn−off to
the Q1 turn−on.
To prevent the overlap of the gate drives during the Q1
turn−off and the Q2 turn−on, the overlap circuit monitors the
voltage at the SW pin. When the PWM input signal goes low,
Q1 begins to turn off (after propagation delay). Before Q2
can turn on, the overlap protection circuit makes sure that
SW has first gone high and then waits for the voltage at the
SW pin to fall from VIN to 1 V. Once the voltage on the SW
pin falls to 1.0 V, Q2 begins turn−on. If the SW pin has not
gone high first, the Q2 turn−on is delayed by a fixed 150 ns.
By waiting for the voltage on the SW pin to reach 1.0 V or
for the fixed delay time, the overlap protection circuit
ensures that Q1 is off before Q2 turns on, regardless of
variations in temperature, supply voltage, input pulse width,
gate charge, and drive current. If SW does not go below
1.0 V after 190 ns, DRVL turns on. This can occur if the
current flowing in the output inductor is negative and flows
through the high−side MOSFET body diode.
Overvoltage Protection
The ADP3121 includes an overvoltage protection (OVP)
feature to protect the CPU from high voltages even before
the main controller has enough VCC to operate. The
ADP3121 looks at the SW node during startup. If the voltage
on SW is greater than the OVP threshold, DRVL is latched
on and DRVH latched off. An OVP on the SW node will
cause DRVL to go high and remain high.
To prevent false triggering of OVP, an input logic
detection latch is set on the first occurrence of either IN or
OD going high. If this second latch is set, then OVP is
enabled. To clear the OVP or the input detected latch, VCC
must fall below UVLO.
Supply Capacitor Selection
For the supply input (VCC) of the ADP3121, a local
bypass capacitor is recommended to reduce the noise and to
supply some of the peak currents that are drawn. Use a
4.7 mF, low ESR capacitor. Multi−layer ceramic chip
(MLCC) capacitors provide the best combination of low
ESR and small size. Keep the ceramic capacitor as close as
possible to the ADP3121.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(CBST) and a diode, as shown in Figure 1. These components
can be selected after the high−side MOSFET is chosen. The
bootstrap capacitor must have a voltage rating that can
handle twice the maximum supply voltage. A minimum
50 V rating is recommended. The capacitor values are
determined by
CBST1 ) CBST2 + 10
QGATE
VGATE
(eq. 1)
CBST1
CBST1 ) CBST2
+
VGATE
VCC * VD
(eq. 2)
where:
QGATE is the total gate charge of the high−side MOSFET at
VGATE.
VGATE is the desired gate drive voltage (usually in the range
of 5.0 V to 10 V, 7.0 V being typical).
VD is the voltage drop across D1.
http://onsemi.com
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet ADP3121.PDF ] | |
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