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ADCLK905 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADCLK905은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 ADCLK905 기능
기능 (ADCLK905 - ADCLK925) Ultrafast ECL Clock / Data Buffers
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ADCLK905 데이터시트, 핀배열, 회로
www.DataSheet4U.com
FEATURES
95 ps propagation delay
7.5 GHz toggle rate
60 ps typical output rise/fall
60 fs random jitter (RJ)
On-chip terminations at both input pins
Extended industrial temperature range: −40°C to +125°C
2.5 V to 3.3 V power supply (VCC VEE)
APPLICATIONS
Clock and data signal restoration and level shifting
Automated test equipment (ATE)
High speed instrumentation
High speed line receivers
Threshold detection
Converter clocking
GENERAL DESCRIPTION
The ADCLK905 (one input, one output), ADCLK907 (dual one
input, one output), and ADCLK925 (one input, two outputs) are
ultrafast clock/data buffers fabricated on the Analog Devices, Inc.,
proprietary XFCB3 silicon germanium (SiGe) bipolar process.
The ADCLK905/ADCLK907/ADCLK925 feature full-swing
emitter coupled logic (ECL) output drivers. For PECL (positive
ECL) operation, bias VCC to the positive supply and VEE to ground.
For NECL (negative ECL) operation, bias VCC to ground and
VEE to the negative supply.
The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate,
10 Gbps data rate, and 60 fs random jitter (RJ).
The inputs have center tapped, 100 Ω, on-chip termination
resistors. A VREF pin is available for biasing ac-coupled inputs.
The ECL output stages are designed to directly drive 800 mV
each side into 50 Ω terminated to VCC − 2 V for a total
differential output swing of 1.6 V.
The ADCLK905/ADCLK907/ADCLK925 are available in
16-lead LFCSP packages.
Ultrafast SiGe
ECL Clock/Data Buffers
ADCLK905/ADCLK907/ADCLK925
TYPICAL APPLICATION CIRCUITS
VREF
VT
VCC
DQ
DQ
VEE
Figure 1. ADCLK905 ECL 1:1 Clock/Data Buffer
VREF1
VT1
D1
D1
VCC
VEE
Q1
Q1
VEE
D2 Q2
D2 Q2
VCC
VT2
VREF2
Figure 2. ADCLK907 ECL Dual 1:1 Clock/Data Buffer
VREF
VT
VCC
Q1
Q1
D
D Q2
Q2
VEE
Figure 3. ADCLK925 ECL 1:2 Clock/Data Fanout Buffer
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.




ADCLK905 pdf, 반도체, 판매, 대치품
wwAwD.DCatLaSKh9ee0t45U./cAomDCLK907/ADCLK925
Parameter
POWER SUPPLY
Supply Voltage Requirement
Power Supply Current
ADCLK905
Negative Supply Current
Positive Supply Current
ADCLK907
Negative Supply Current
Positive Supply Current
ADCLK925
Negative Supply Current
Positive Supply Current
Power Supply Rejection1
Output Swing Supply Rejection2
1 Change in TPD per change in VCC.
2 Change in output swing per change in VCC.
Symbol Min
VCC − VEE 2.375
IVEE
IVCC
IVEE
IVCC
IVEE
IVCC
PSRVCC
PSRVCC
Typ
24
25
47
48
48
50
94
96
29
31
76
77
3
26
Max
3.63
40
63
80
126
51
97
Unit
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ps/V
dB
Conditions
2.5 V − 5% to 3.3 V + 10%
Static
VCC − VEE = 2.5 V
VCC − VEE = 3.3 V ± 10%
VCC − VEE = 2.5 V
VCC − VEE = 3.3 V ± 10%
VCC − VEE = 2.5 V
VCC − VEE = 3.3 V ± 10%
VCC − VEE = 2.5 V
VCC − VEE = 3.3 V ± 10%
VCC − VEE = 2.5 V
VCC − VEE = 3.3 V ± 10%
VCC − VEE = 2.5 V
VCC − VEE = 3.3 V ± 10%
VCC − VEE = 3.0 V ± 20%
VCC − VEE = 3.0 V ± 20%
Rev. 0 | Page 4 of 16

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ADCLK905 전자부품, 판매, 대치품
www.DataSheet4U.com
ADCLK905/ADCLK907/ADCLK925
Pin No.
10
11
12
15
16
Heat Sink
Mnemonic
Q2
Q1
Q1
VREF1
VT1
NC
Description
Noninverting Output 2.
Inverting Output 1.
Noninverting Output 1.
Reference Voltage 1. Reference voltage for biasing ac-coupled inputs, Channel 1.
Center Tap 1. Center tap of 100 Ω input resistor, Channel 1.
No Connect. The metallic back surface of the package is not electrically connected to any part of the circuit.
It can be left floating for optimal electrical isolation between the package handle and the substrate of the die.
It can also be soldered to the application board if improved thermal and/or mechanical stability is desired.
Exposed metal at the corners of the package is connected to this back surface. Allow sufficient clearance
to vias and other components.
D1
D2
NC 3
NC 4
PIN 1
INDICATOR
ADCLK925
TOP VIEW
(Not to Scale)
12 Q1
11 Q1
10 Q2
9 Q2
NC = NO CONNECT
Figure 6. ADCLK925 Pin Configuration
Table 6. Pin Function Descriptions for 1:2 ADCLK925 Buffer
Pin No. Mnemonic Description
1D
Noninverting Input.
2D
Inverting Input.
3, 4, 5, 6 NC
No Connect. No physical connection to the die.
7, 14
VEE
Negative Supply Voltage.
8, 13
VCC
Positive Supply Voltage.
9 Q2
Inverting Output 2.
10 Q2
Noninverting Output 2.
11 Q1
Inverting Output 1.
12 Q1
Noninverting Output 1.
15 VREF
16 VT
Reference Voltage. Reference voltage for biasing ac-coupled inputs.
Center Tap. Center tap of 100 Ω input resistor.
Heat Sink NC
No Connect. The metallic back surface of the package is not electrically connected to any part of the circuit.
It can be left floating for optimal electrical isolation between the package handle and the substrate of the die.
It can also be soldered to the application board if improved thermal and/or mechanical stability is desired.
Exposed metal at the corners of the package is connected to this back surface. Allow sufficient clearance
to vias and other components.
Rev. 0 | Page 7 of 16

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관련 데이터시트

부품번호상세설명 및 기능제조사
ADCLK905

(ADCLK905 - ADCLK925) Ultrafast ECL Clock / Data Buffers

Analog Devices
Analog Devices
ADCLK907

(ADCLK905 - ADCLK925) Ultrafast ECL Clock / Data Buffers

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