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부품번호 FXL3SD206 기능
기능 Two-Port SDIO Mux/Demux Level-Shifting Voltage Translator
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FXL3SD206 데이터시트, 핀배열, 회로
www.DataSheet4U.com
March 2009
FXL3SD206
Level Shifting Voltage Translator
Two-Port SDIO MUX/DEMUX with Three Configurable Power
Supplies for SDIO Device Port Expansion
Features
ƒ Bi-Directional Interface between Two Levels:
1.65 to 3.6V
ƒ Fully Configurable: Inputs and Outputs Track VDD
ƒ Flexible and Programmable VDD of B and C Ports
ƒ Non-Preferential Power-up; either VDD Can Power
Up First
ƒ Output Remains in 3-State until Active VDD Level is
Reached
ƒ Output Switches to 3-state if either VDD is at GND
ƒ Power-off Protection
ƒ Bus-Hold on Data Input Eliminates the Need for
SDIO Pull-up Resistors
ƒ 2:1 MUX/DEMUX of SDIO Devices in 24-Terminal
Micro-MLP Package (2.5mm x 3.4mm)
ƒ Direction Control is Automatic
ƒ Power Switching Time (VDD_HI to VDD_LO or Reverse)
is Less than 1.7µs
ƒ 60Mbps Throughput
ƒ ESD Protection Exceeds:
‚ 12KV HBM (A, B, and C port I/O to GND)
(per JESD22-A114)
‚ 1KV CDM (per ESD STM5.3)
Applications
ƒ SDIO Devices
ƒ Cell Phone, PDA, Digital Camera, Portable GPS
Description
FXL3SD206 is a voltage translator with multiplexing and
de-multiplexing functions for SDIO devices. It is
designed for voltage translation over a wide range of
input and output levels, from 1.65V to 3.6V.
The multiplexing/de-multiplexing function of this device
allows expansion of a host SDIO interface to two SDIO
peripheral devices. When selected, each SDIO peripheral
can communicate with the host through the same host
interface. An alternative application allows two host
devices to interface with a single SDIO peripheral.
Port A is intended to connect to a host device and the
voltage level tracks the VDDA. Ports B and C are
intended to connect to peripheral devices. Peripheral
I/O voltage levels track either VDD_HI or VDD_LO as
determined by the VDD_SEL pin. During normal
operation, VDD_HI must be greater than or equal to
VDD_LO. The CH_SEL, VDD_SEL, and OE pins are
referenced to VDD_CON. Channel communication from
either Port A to Port B or Port A to Port C is controlled
by the CH_SEL pin.
The selected channel remains in 3-state until the VDD of
each side reaches an active level and the OE pin
reaches a valid high. Internal power-down circuitry
places the selected channel of the device in 3-state if
either side VDD removed.
The direction of data is controlled automatically by the
device. No direction control pin is required. The device
senses input signals on any port automatically and
transfers the data to the corresponding output.
Ordering Information
Part Number
Operating
Temperature Range
FXL3SD206UMX
-40 to +85°C
Eco
Status
Green
Package
24-Pin, Micro-MLP, Quad, .6mm Thick,
2.5mm x 3.4mm Body
Packing
Method
Tape & Reel
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2009 Fairchild Semiconductor Corporation
FXL3SD206 • Rev. 1.0.0
www.fairchildsemi.com




FXL3SD206 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
Function Diagram
Figure 4. Function Diagram
Function Table
OE CH_SEL VDD_SEL
Output
LOW
Don’t Care
Don’t Care
3-State
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
HIGH
LOW
HIGH
LOW
Normal operation; Port A to Port B channel
selected; Port B tracks VDD_HI level
Normal operation; Port A to Port B channel
selected; Port B tracks VDD_LO level
Normal operation; Port A to Port C channel
selected; Port C tracks VDD_HI level
Normal operation; Port A to Port C channel
selected; Port C tracks VDD_LO level
Note:
1. VDD_CON: This is a power supply pin that is used by the three control pins (VDD_SEL, CH_SEL, and OE).
In single host mode, VDD_CON should be tied to the same supply as the VDDA pin. In dual host mode,
VDD_CON should be tied to the same supply as either the VDD_HI or the VDD_LO pin, depending upon which
host is used to drive the control pins.
© 2009 Fairchild Semiconductor Corporation
FXL3SD206 • Rev. 1.0.0
4
www.fairchildsemi.com

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FXL3SD206 전자부품, 판매, 대치품
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DC Electrical Characteristics
TA=-40°C to 85°C unless otherwise specified.
Symbol Parameter
Condition
VDD_A,
VDD_n, (V)
Min.
Max. Units
VIHA Data Inputs Dn_A, CMD_A, CLK_A, 1.65 – 3.6 0.6 x VDD_A
VIHB
High Level Input
Data Inputs Dn_BC, CMD_B,
CLK_BC, CH_SEL=H
VIHC
Voltage(6)
Data Inputs Dn_BC, CMD_C,
CLK_BC, CH_SEL=L
1.65 – 3.6 0.6 x VDD_n
1.65 – 3.6 0.6 x VDD_n
V
V
V
VIH
VILA
VILB
Low Level Input
VILC
Voltage(6)
OE, VDD_SEL, CH_SEL
Data Inputs Dn_A, CMD_A, CLK_A,
Data Inputs Dn_BC, CMD_B,
CLK_BC, CH_SEL=H
Data Inputs Dn_BC, CMD_C,
CLK_BC, CH_SEL=L
1.65 – 3.6 0.6 x VDD_CON
1.65 – 3.6
0.35 x VDD_A
1.65 -3.6
0.35 x VDD_n
1.65 -3.6
0.35 x VDD_n
V
V
V
V
VIL
VOHA
VOHB
VOHC
VOLA
VOLB
VOLC
OE, VDD_SEL, CH_SEL
High Level Output
Voltage(6, 7)
Low Level Output
Voltage(6, 7)
Data Outputs Dn_A, CMD_A,
CLK_A, IHOLD=-20µA
Data Outputs Dn_BC, CMD_B,
CLK_BC, CH_SEL=H, IHOLD=-20µA
Data Outputs Dn_BC, CMD_B,
CLK_BC, CH_SEL=L, IHOLD=-20µA
Data Outputs Dn_A, CMD_A,
CLK_A, IHOLD=+20µA
Data Outputs Dn_BC, CMD_B,
CLK_BC, CH_SEL=H, IHOLD=+20µA
Data Outputs Dn_BC, CMD_B,
CLK_BC, CH_SEL=L, IHOLD=+20µA
1.65 – 3.6
1.65 – 3.6 0.75 x VDD_A
1.65 – 3.6 0.75 x VDD_n
1.65 – 3.6 0.75 x VDD_n
1.65 – 3.6 0.25 x VDD_A
1.65 – 3.6 0.25 x VDD_n
1.65 – 3.6 0.25 x VDD_n
0.35 x
VDD_CON
V
V
V
V
V
V
V
Notes:
6. Port B and Port C share the same data and clock pin, and VDD_n refers to VDD_HI or VDD_LO, whichever is
selected. During normal operation, VDD_HI must be greater than or equal to VDD_LO.
7. This is the output voltage for static conditions. Dynamic drive specifications are given in “Dynamic Output
Electrical Characteristics.
© 2009 Fairchild Semiconductor Corporation
FXL3SD206 • Rev. 1.0.0
7
www.fairchildsemi.com

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부품번호상세설명 및 기능제조사
FXL3SD206

Two-Port SDIO Mux/Demux Level-Shifting Voltage Translator

Fairchild Semiconductor
Fairchild Semiconductor

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