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UM10336 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 UM10336
기능 User Manual
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UM10336
P89LPC9201/9211/922A1/9241/9251 User manual
Rev. 01 — 22 April 2009
User manual
Document information
Info Content
Keywords
P89LPC9201/9211/922A1/9241/9251
Abstract
Technical information for the P89LPC9201/9211/922A1/9241/9251 device




UM10336 pdf, 반도체, 판매, 대치품
NXP Semiconductors
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UM10336
P89LPC9201/9211/922A1/9241/9251 User manual
P89LPC922A1
P0.0/CMP2/KBI0 1
P1.7 2
P1.6 3
P1.5/RST 4
VSS 5
P3.1/XTAL1 6
P3.0/XTAL2/CLKOUT 7
P1.4/INT1 8
P1.3/INT0/SDA 9
P1.2/T0/SCL 10
20 P0.1/CIN2B/KBI1
19 P0.2/CIN2A/KBI2
18 P0.3/CIN1B/KBI3
17 P0.4/CIN1A/KBI4
16 P0.5/CMPREF/KBI5
15 VDD
14 P0.6/CMP1/KBI6
13 P0.7/T1/KBI7
12 P1.0/TXD
11 P1.1/RXD
002aae427
Fig 3. P89LPC922A1 DIP20 pin configuration
1.2 Pin description
Table 1. Pin description
Symbol
Pin
Type Description
P0.0 to P0.7
P0.0/CMP2/
KBI0
P0.1/CIN2B/
KBI1/AD10
P0.2/CIN2A/
KBI2/AD11
TSSOP20,
DIP20
I/O
1 I/O
O
I
20 I/O
I
I
I
19 I/O
I
I
I
Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset
Port 0 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 0 pins as inputs and outputs depends upon the
port configuration selected. Each port pin is configured independently. Refer to
Section 5.1 “Port configurations” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt trigger inputs.
Port 0 also provides various special functions as described below:
P0.0 — Port 0 bit 0.
CMP2 — Comparator 2 output
KBI0 — Keyboard input 0.
P0.1 — Port 0 bit 1.
CIN2B — Comparator 2 positive input B.
KBI1 — Keyboard input 1.
AD10 — ADC1 channel 0 analog input. (P89LPC9241/9251)
P0.2 — Port 0 bit 2.
CIN2A — Comparator 2 positive input A.
KBI2 — Keyboard input 2.
AD11 — ADC1 channel 1 analog input. (P89LPC9241/9251)
UM10336_1
User manual
Rev. 01 — 22 April 2009
© NXP B.V. 2009. All rights reserved.
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UM10336
P89LPC9201/9211/922A1/9241/9251 User manual
1.3 Logic symbols
KBI0
KBI1
KBI2
KBI3
KBI4
KBI5
KBI6
KBI7
CLKOUT
CMP2
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
CMP1
T1
XTAL2
XTAL1
PORT 0
PORT 3
Fig 4. P89LPC9201/9211/922A1 logic symbol
VDD VSS
P89LPC9201/
9211/922A1
PORT 1
TXD
RXD
T0
INT0
INT1
RST
SCL
SDA
002aae423
VDD VSS
DAC1
AD10
AD11
AD12
AD13
KBI0
KBI1
KBI2
KBI3
KBI4
KBI5
KBI6
KBI7
CLKOUT
CMP2
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
CMP1
T1
XTAL2
XTAL1
PORT 0
PORT 3
Fig 5. P89LPC9241/9251 logic symbol
P89LPC9241/
9251
PORT 1
TXD
RXD
T0
INT0
INT1
RST
SCL
SDA
002aae424
UM10336_1
User manual
Rev. 01 — 22 April 2009
© NXP B.V. 2009. All rights reserved.
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