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LTC2461 데이터시트 PDF




Linear Technology Corporation에서 제조한 전자 부품 LTC2461은 전자 산업 및 응용 분야에서
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부품번호 LTC2461 기능
기능 (LTC2461 / LTC2463) 16-Bit I2C Delta Sigma ADCs
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LTC2461 데이터시트, 핀배열, 회로
www.DataSheet4U.com
FEATURES
n 16-Bit Resolution, No Missing Codes
n Internal Reference, High Accuracy 10ppm/°C (Max)
n Single-Ended (LTC2461) or Differential (LTC2463)
n 2LSB Offset Error (Typ)
n 0.01% Gain Error (Typ)
n 60 Conversions Per Second
n Single Conversion Settling Time for Multiplexed
Applications
n 1.5mA Supply Current
n 200nA Sleep Current
n Internal Oscillator—No External Components
Required
n 2-Wire I2C Interface with Two Addresses Plus One
Global Address for Synchronization
n Ultra-Tiny, 12-Lead, 3mm × 3mm DFN and MSOP
Packages
APPLICATIONS
n System Monitoring
n Environmental Monitoring
n Direct Temperature Measurements
n Instrumentation
n Data Acquisition
n Embedded ADC Upgrades
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378.
LTC2461/LTC2463
Ultra-Tiny, 16-Bit I2C ΔΣ
ADCs with 10ppm/°C Max
Precision Reference
DESCRIPTION
The LTC®2461/LTC2463 are ultra tiny, 16-Bit analog-to-
digital converters with an integrated precision reference.
They use a single 2.7V to 5.5V supply and communicate
through an I2C Interface. The LTC2461 is single-ended
with a 0V to 1.25V input range and the LTC2463 is dif-
ferential with a 1.25V input range. Both ADCs include a
1.25V integrated reference with 2ppm/°C drift perfor-
mance and 0.1% initial accuracy. The converters are
available in a 12-pin 3mm × 3mm DFN package or an
MSOP-12 package. They include an integrated oscillator
and perform conversions with no latency for multiplexed
applications. The LTC2461/LTC2463 include a proprietary
input sampling scheme that reduces the average input
current several orders of magnitude when compared to
conventional delta sigma converters.
Following a single conversion, the LTC2461/LTC2463
automatically power down the converter and can also be
configured to power down the reference. When both the
ADC and reference are powered down, the supply current
is reduced to 200nA.
The LTC2461/LTC2463 can sample at 60 conversions per
second and, due to the very large oversampling ratio,
have extremely relaxed antialiasing requirements. Both
include continuous internal offset and fullscale calibration
algorithms which are transparent to the user, ensuring ac-
curacy over time and the operating temperature range.
TYPICAL APPLICATION
2.7V TO 5.5V
0.1μF
0.1μF
0.1μF
10μF
0.1μF
REFOUT
COMP VCC
10k 10k
IN+ LTC2463 SCL I2C
INSDA INTERFACE
10k
R
0.1μF
REF
A0
GND
24613 TA01a
1.2520
VREF vs Temperature
1.2515
1.2510
1.2505
1.2500
1.2495
1.2490
1.2485
1.2480
–50 –30 –10 10 30 50
TEMPERATURE (°C)
70 90
24613 TA01b
24613f
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LTC2461 pdf, 반도체, 판매, 대치품
wwwL.DTataCShe2et44U.c6om1/LTC2463
I C INPUTS AND OUTPUTS2
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Notes 2, 7)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VIH High Level Input Voltage
VIL Low Level Input Voltage
l 0.7VCC
l
0.3VCC
V
V
II Digital Input Current
l –10
10 μA
VHYS
Hysteresis of Schmidt Trigger Inputs
(Note 3)
l 0.05VCC
V
VOL
Low Level Output Voltage (SDA)
I = 3mA
IIN Input Leakage
0.1VCC ≤ VIN ≤ 0.9VCC
CI Capacitance for Each I/O Pin
l
l
l 10
0.4 V
1 μA
pF
CB Capacitance Load for Each Bus Line
l 400 pF
VIH(A0)
High Level Input Voltage for Address Pin
l 0.95VCC
V
VIL(A0)
Low Level Input Voltage for Address Pin
l
0.05VCC
V
I2C TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 7)
SYMBOL
tCONV
fSCL
tHD(SDA,STA)
tLOW
tHIGH
tSU(STA)
tHD(DAT)
tSU(DAT)
tr
tf
tSU(STO)
tBUF
tOF
tSP
PARAMETER
CONDITIONS
Conversion Time
SCL Clock Frequency
Hold Time (Repeated) START Condition
LOW Period of the SCL Pin
HIGH Period of the SCL Pin
Set-Up Time for a Repeated START Condition
Data Hold Time
Data Set-Up Time
Rise Time for SDA, SCL Signals
(Note 6)
Fall Time for SDA, SCL Signals
(Note 6)
Set-Up Time for STOP Condition
Bus Free Time Between a Stop and Start Condition
Output Fall Time VIHMIN to VILMAX
Bus Load CB = 10pF to
400pF (Note 6)
Input Spike Suppression
MIN
l 13
l0
l 0.6
l 1.3
l 0.6
l 0.6
l0
l 100
l 20 + 0.1CB
l 20 + 0.1CB
l 0.6
l 1.3
l 20 + 0.1CB
l
TYP
16.6
MAX UNITS
23 ms
400 kHz
μs
μs
μs
μs
0.9 μs
ns
300 ns
300 ns
μs
μs
250 ns
50 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND. VCC = 2.7V to 5.5V
unless otherwise specified.
Note 3: Guaranteed by design, not subject to test.
Note 4: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
Guaranteed by design and test correlation.
Note 5: Input sampling current is the average input current drawn from
the input sampling network while the LTC2461/LTC2463 are converting.
Note 6: CB = capacitance of one bus line in pF.
Note 7: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 8: A positive current is flowing into the DUT pin.
Note 9: Voltage temperature coefficient is calculated by dividing the
maximum change in output voltage by the specified temperature range.
24613f
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LTC2461 전자부품, 판매, 대치품
www.DataSheet4U.com
LTC2461/LTC2463
PIN FUNCTIONS
REFOUT (Pin 1): Reference Output Pin. Nominally 1.25V,
this voltage sets the fullscale input range of the ADC. For
noise and reference stability connect to a 0.1μF capacitor
tied to GND. This capacitor value must be less than or
equal to the capacitor tied to the reference compensation
pin (COMP). REFOUT cannot be overdriven by an external
reference. For applications that require an input range
greater than 0V to 1.25V, please refer to the LTC2451/
LTC2453.
COMP (Pin 2): Internal Reference Compensation Pin. For
low noise and reference stability, tie a 0.1μF capacitor to
GND.
A0 (Pin 3): Chip Address Control Pin. The A0 pin can be
tied to GND or VCC. If A0 is tied to GND, the LTC2461/
LTC2463 I2C address is 0010100. If A0 is tied to VCC, the
LTC2461/LTC2463 I2C address is 1010100.
GND (Pins 4, 7, 11): Ground. Connect directly to the
ground plane through a low impedance connection.
SCL (Pin 5): Serial Clock Input of the I2C Interface. The
LTC2461/LTC2463 can only act as a slave and the SCL pin
only accepts external serial clock. Data is shifted into the
SDA pin on the rising edges of SCL and output through
the SDA pin on the falling edges of SCL.
SDA (Pin 6): Bidirectional Serial Data Line of the I2C Inter-
face. The conversion result is output through the SDA pin.
The pin is high impedance unless the LTC2461/LTC2463
is in the data output mode. While the LTC2461/LTC2463
is in the data output mode, SDA is an open drain pull
down (which requires an external 1.7k pull-up resistor
to VCC).
REF(Pin 8): Negative Reference Input to the ADC. The
voltage on this pin sets the zero input to the ADC. This
pin should tie directly to ground or the ground sense of
the input sensor.
IN+ (LTC2463), IN (LTC2461) (Pin 9): Positive input volt-
age for the LTC2463 differential device. ADC input for the
LTC2461 single-ended device.
IN(LTC2463), GND (LTC2461) (Pin 10): Negative input
voltage for the LTC2463 differential device. GND for the
LTC2461 single-ended device.
VCC (Pin 12): Positive Supply Voltage. Bypass to GND with
a 10μF capacitor in parallel with a low-series-inductance
0.1μF capacitor located as close to pin 12 as possible.
Exposed Pad (Pin 13 – DFN Package): Ground. Connect
directly to the ground plane through a low impedance
connection.
24613f
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