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PDF BUK9MJJ-55PTT Data sheet ( Hoja de datos )
| Número de pieza | BUK9MJJ-55PTT | |
| Descripción | Dual TrenchPLUS Logic Level FET | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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BUK9MJJ-55PTT
www.DataSheet4U.com
Dual TrenchPLUS logic level FET
Rev. 01 — 14 May 2009
Product data sheet
1. Product profile
1.1 General description
Dual N-channel enhancement mode field-effect power transistor in SO20. Device is
manufactured using NXP High-Performance (HPA) TrenchPLUS technology, featuring
very low on-state resistance, integrated current sensing transistors and over temperature
protection diodes.
1.2 Features and benefits
Integrated current sensors
Integrated temperature sensors
1.3 Applications
Lamp switching
Motor drive systems
Power distribution
Solenoid drivers
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
Static characteristics, FET1 and FET2
RDSon
drain-source
on-state resistance
VGS = 5 V; ID = 10 A;
Tj = 25 °C; see Figure 16;
see Figure 17
ID/Isense ratio of drain current Tj = 25 °C; VGS = 5 V; see
to sense current
Figure 18
V(BR)DSS drain-source
Tj = 25 °C; VGS = 0 V;
breakdown voltage ID = 250 µA
Min Typ Max Unit
- 13 15 mΩ
5850 6500 7150 A/A
55 - - V
1 page  
NXP Semiconductors
www.DataSheet4U.com
BUK9MJJ-55PTT
Dual TrenchPLUS logic level FET
102
IAL
(A)
10
1
003aab924
(1)
(2)
(3)
10-1
10-3
10-2
10-1
1 10
tAL (ms)
Fig 4. Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time, FET1 and
FET2
5. Thermal characteristics
Table 5.
Symbol
Rth(j-sp)
Rth(j-a)
Thermal characteristics
Parameter
Conditions
thermal resistance from FET1
junction to solder point FET2
thermal resistance from mounted on a printed-circuit board; Both
junction to ambient
channels conducting; zero heat sink area;
see Figure 5; see Figure 6
mounted on a printed-circuit board; Both
channels conducting; 200 mm2 copper
heat sink area; see Figure 5; see Figure 7
mounted on a printed-circuit board; Both
channels conducting; 400 mm2 copper
heat sink area; see Figure 5; see Figure 8
mounted on a printed-circuit board; One
channel conducting; zero heat sink area;
see Figure 5; see Figure 6
mounted on a printed-circuit board; One
channel conducting; 200 mm2 copper heat
sink area; see Figure 5; see Figure 7
mounted on a printed-circuit board; One
channel conducting; 400 mm2 copper heat
sink area; see Figure 5; see Figure 8
Min Typ Max Unit
- - 28 K/W
- - 28 K/W
- 73 - K/W
- 60 - K/W
- 51 - K/W
- 105 - K/W
- 90 - K/W
- 78 - K/W
BUK9MJJ-55PTT_1
Product data sheet
Rev. 01 — 14 May 2009
© NXP B.V. 2009. All rights reserved.
5 of 15
5 Page 
NXP Semiconductors
www.DataSheet4U.com
BUK9MJJ-55PTT
Dual TrenchPLUS logic level FET
5
VGS
(V)
4
3
2
1
0
0
003aac413
VDS = 14 V
VDS = 44 V
10 20 30 40
QG (nC)
104
C
(p F )
103
102
003aac409
Cis s
Cos s
Crs s
10
10-1
1
10 102
VDS (V)
Fig 20. Gate-source voltage as a function of turn-on
gate charge; typical values, FET1 and FET2
50
IS
(A)
40
Fig 21. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values, FET1 and FET2
003aac418
30 150 °C
Tj = 25 °C
20
10
0
0 0.5 1 1.5 VSD(V) 2
Fig 22. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values, FET1
and FET2
BUK9MJJ-55PTT_1
Product data sheet
Rev. 01 — 14 May 2009
© NXP B.V. 2009. All rights reserved.
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