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기능 HDMI 1.3 transmitter
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TDA9984A 데이터시트, 핀배열, 회로
www.DataSheet4U.com
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
Rev. 04 — 15 January 2009
Product data sheet
1. General description
The TDA9984A is a High-Definition Multimedia Interface (HDMI) v. 1.3 transmitter with
embedded 1080p upscaling functionality. It is backward compatible DVI 1.0 and can be
connected to any DVI 1.0 and HDMI sink. It allows mixing a 3 × 8-bit RGB or YCbCr video
stream with a pixel rate up to 150 MHz together with up to 4 × I2S-bus or one S/PDIF
audio streams with an audio sampling rate up to 192 kHz. It supports Gamut boundary
description (xvYCC), as well as HD audio, both HDMI 1.3 features.
A programmable upscaling block allows creating a 1080p output from a standard definition
input. An intrafield deinterlacer is included in the scaler.
In order to be compatible with most applications, and thanks to the integration of a fully
programmable input formatter and color space conversion block, the video input formats
accepted also include YCbCr 4 : 4 : 4 (up to 3 × 8-bit), YCbCr 4 : 2 : 2 semi-planar (up to
2 × 12-bit) and YCbCr 4 : 2 : 2 compliant with ITU656 (up to 1 × 12-bit). In case of
ITU656-like format, the input pixel clock can be made active on both edges.
The TDA9984A includes a HDCP 1.2 compliant cipher block. The HDCP key are stored
internally in a non-volatile OTP memory for maximum security.
The TDA9984A includes a true I2C-bus master interface for DDC-bus communication for
EDID purpose and HDCP purpose.
The TDA9984A can be controlled by an I2C-bus interface.
2. Features
I 3 × 8-bit video data input buses; CMOS and LV-TTL compatible
I Horizontal synchronization, vertical synchronization and data enable inputs or VREF,
HREF and FREF inputs which can be used for synchronization
I Pixel rate clock input can be made active on one or both edges; selectable via I2C-bus
I 4 × I2S-bus audio input channels, one S/PDIF channel; audio data rate up to 192 kHz
per input for both standards
I Dolby-True HD and DTS-HD High bit rate audio support through the use of the HBR
interface
I 250 MHz to 1.50 GHz TMDS transmitter operation
I Programmable input formatter and upsampler/interpolator allows input of any of the
4 : 4 : 4 or 4 : 2 : 2 semi-planar and 4 : 2 : 2 ITU656-like formats




TDA9984A pdf, 반도체, 판매, 대치품
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VPP
VDDD(3V3)
VDDC(1V8)
VDDA(PLL)(1V8)
VDDH(3V3) VDDA(FRO)(3V3)
VDDA(PLL)(3V3) RST_N
TM
AP0 to AP7
ACLK
3
21
13, 48, 71 59, 74
28, 34
23
4 to 11
AUDIO
PROCESSING
AUDIO
FIFO
AUDIO CONTENT
AUDIO INFO-FRAME
12
CTS/N
ACR
16, 45
DATA
ISLAND
PACKET
INSERTION
38 42
HARD
RESET
VIDEO INFO-FRAME
A1 A0 I2C_SCL I2C_SDA DDC_SDA DDC_SCL
40 41
43 44
19 20
I2C-BUS
SLAVE
DDC BUS
MASTER
INTERRUPT
GENERATION
I2C-BUS REGISTERS
HPD
MANAGEMENT
RxSENSE
VCLK 66
CLOCK
MANAGMENT
OTHER INFO-FRAME
VHREF GENERATOR
VPA[7:0]
VPB[7:0]
VPC[7:0]
VSYNC/VREF
HSYNC/HREF
DE/FREF
68 to 70
75 to 79
57, 58
61 to 65,
67
49 to 56
2
1
80
VIDEO
INPUT
PROCESSOR
3 × 8-bit RGB or YCbCr 4 : 4 : 4
2 × 12-bit YCbCr 4 : 2 : 2 semi-planar
1 × 12-bit YCbCr 4 : 2 : 2 ITU656
2 × 12-bit YCbCr 4 : 2 : 2 semi-planar
1 × 12-bit YCbCr 4 : 2 : 2 ITU656
UPSCALER
4:2:2
UPSAMPLER
4:2:2
to
4:4:4
COLOR
SPACE
CONVERTER
RGB to YCbCr
YCbCr to RGB
DOWN-
SAMPLER
4:4:4
to
4:2:2
14, 47,
25, 31,
72
60, 73
37
22
39
46, 15
VSSD
VSSC
VSSH
VSSA(FRO)(3V3) VSSA(PLL)(3V3) VSSA(PLL)(1V8)
OTP
MEMORY
KEYS
HDCP
PROCESSING
TMDS
SERIALIZER
TDA9984AHW
17 INT
18
HPD
27
TXC+
26 TXC
30
TX0+
29 TX0
33 TX1+
32 TX1
36
TX2+
35 TX2
24 EXT_SWING
001aag595
The device can handle HDCP based on 1.2 features.
Fig 1. Block diagram

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TDA9984A 전자부품, 판매, 대치품
www.DNatXaSPheSete4Um.coicmonductors
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
Table 3. Pin description …continued
Symbol
Pin Type[1] Description
VDDD(3V3)
VPC[7]
48 P
49 I
digital supply voltage for I/O ports (3.3 V)
video port C input bit 7 (MSB)
VPC[6]
50 I
video port C input bit 6
VPC[5]
51 I
video port C input bit 5
VPC[4]
52 I
video port C input bit 4
VPC[3]
53 I
video port C input bit 3
VPC[2]
54 I
video port C input bit 2
VPC[1]
55 I
video port C input bit 1
VPC[0]
56 I
video port C input bit 0 (LSB)
VPB[7]
57 I
video port B input bit 7 (MSB)
VPB[6]
58 I
video port B input bit 6
VDDC(1V8)
VSSC
VPB[5]
59 P
60 G
61 I
supply voltage for digital core (1.8 V)
ground for digital core
video port B input bit 5
VPB[4]
62 I
video port B input bit 4
VPB[3]
63 I
video port B input bit 3
VPB[2]
64 I
video port B input bit 2
VPB[1]
65 I
video port B input bit 1
VCLK
66 I
video pixel clock input
VPB[0]
67 I
video port B input bit 0 (LSB)
VPA[7]
68 I
video port A input bit 7 (MSB)
VPA[6]
69 I
video port A input bit 6
VPA[5]
70 I
video port A input bit 5
VDDD(3V3)
VSSD
VSSC
VDDC(1V8)
VPA[4]
71 P
72 G
73 G
74 P
75 I
digital supply voltage for I/O ports (3.3 V)
digital ground for I/O ports
ground for digital core
supply voltage for digital core (1.8 V)
video port A input bit 4
VPA[3]
76 I
video port A input bit 3
VPA[2]
77 I
video port A input bit 2
VPA[1]
78 I
video port A input bit 1
VPA[0]
79 I
video port A input bit 0
DE/FREF
80 I
video data enable or field reference input
[1] P = Power supply; G = Ground; I = Input; O = Output.
TDA9984A_4
Product data sheet
Rev. 04 — 15 January 2009
© NXP B.V. 2009. All rights reserved.
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TDA9984A

HDMI 1.3 transmitter

NXP Semiconductors
NXP Semiconductors

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