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부품번호 TDA9981A 기능
기능 HDMI Transmitter Up To 150 MHz Pixel Rate
제조업체 NXP Semiconductors
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TDA9981A 데이터시트, 핀배열, 회로
www.DataSheet4U.com
TDA9981A
HDMI transmitter up to 150 MHz pixel rate with 3 × 8-bit video
inputs and 4 × I2S-bus with S/PDIF
Rev. 01 — 19 May 2008
Product data sheet
1. General description
The TDA9981A is an HDMI transmitter (which also supports DVI) that enables a 3 × 8-bit
RGB or YCBCR video stream (with a pixel rate up to 150 MHz for the TDA9981AHL/15
version), up to 4 I2S-bus audio streams (with an audio sampling rate up to 192 kHz) and
the additional information required by all the HDMI 1.2a standards.
In order to be compatible with most applications, the TDA9981A integrates a full
programmable input formatter and color space conversion block. The video input formats
accepted are YCBCR 4 : 4 : 4 (up to 3 × 8-bit), YCBCR 4 : 2 : 2 semi-planar (up to
2 × 12-bit), YCBCR 4 : 2 : 2 compliant with ITU656 and ITU656-like (up to 1 × 12-bit).
For ITU656-like formats, double edges are supported so that data can be sampled on
rising and falling edges.
The TDA9981A also includes a HDCP 1.1-compliant cipher block. The HDCP key set is
stored internally in a One Time Programmable (OTP) non-volatile memory for maximum
security.
The device can be controlled via an I2C-bus interface.
2. Features
s 3 × 8-bit video data input bus, CMOS and LV-TTL compatible
s Horizontal synchronization, vertical synchronization and Data Enable (DE) inputs or
VREF, HREF and FREF could be used for input data synchronization
s Pixel rate clock input can be made active on one or both edges (selectable by I2C-bus)
s The TDA9981A has 4 I2S-bus audio input channels and 1 S/PDIF channel; audio
sampling rate up to 192 kHz
s 250 MHz to 1.50 GHz HDMI transmitter operation
s Programmable input formatter and upsampler/interpolator allows input of any of the
4 : 4 : 4, 4 : 2 : 2 semi-planar, 4 : 2 : 2 ITU656 and ITU656-like formats
s Programmable color space converter:
x RGB to YCBCR
x YCBCR to RGB
s Deals with multiple levels of HDCP receivers and repeaters
s Internal SHA-1 calculation
s Controllable via I2C-bus
s Low power dissipation




TDA9981A pdf, 반도체, 판매, 대치품
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HPD 18
AP7 to AP0
ACLK
4 to 11
12
VPA[7:0]
VPB[7:0]
VPC[7:0]
VSYNC/VREF
HSYNC/HREF
DE/FREF
VCLK
68 to 70,
75 to 79
57 and 58,
61 to 65,
67
49 to 56
2
1
80
66
HPD
MANAGEMENT
RST_N
42
HARD
RESET
VPP
VDDC(1V8)
VDDH(3V3)
VDDD(3V3) VDDA(FRO_3V3) VDDA(PLL_3V3)
I2C_SCL I2C_SDA
A0 A1
3
13, 48, 16, 45, 23
28, 34 38
71 59, 74
43 44 41 40
I2C-BUS
SLAVE
DDC-BUS
AUDIO
PROCESSING
INFORMATION
FRAMES AND
PACKETS
VIDEO
INPUT
PROCESSOR
DATA
ISLAND
PACKET
VIDEO PROCESSING
RGB
YCBCR 4 : 4 : 4
3 × 8-bit
UPSAMPLING
FROM
4:2:2
TO
4 : 4 : 4(1)
COLOR
SPACE
CONVERTER
RGB TO YUV
YUV TO RGB
(4 : 4 : 4)(1)
YCBCR 4 : 2 : 2
ITU656 or ITU656-like
14, 47,
72
VSSD
2 × 12-bit
or 1 × 12-bit
15, 60,
73
22
39
VSSC
VSSA(FRO_3V3) VSSA(PLL_3V3)
IRQ
GENERATION
DOWNSAMPLING
FROM
4:4:4
TO
4 : 2 : 2(1)
OTP
MEMORY
KEYS
HDMI
SERIALIZER
HDCP
25, 31,
37
46
VSSH
VSSA(PLL_1V8)
TDA9981A
21
TM
24
EXT_SWING
20 DDC_SCL
19
DDC_SDA
17
INT
27
TXC+
26 TXC
30 TX0+
29 TX0
33
TX1+
32 TX1
36 TX2+
35
TX2
001aah914
(1) Block can be bypassed.
Fig 1. Block diagram

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TDA9981A 전자부품, 판매, 대치품
www.DNatXaSPheSete4Um.coicmonductors
TDA9981A
150 MHz pixel rate HDMI transmitter
TDA9981A_1
Product data sheet
Table 4. Pin description …continued
Symbol
Pin Type[1] Description
I2C_SCL
43 I
I2C-bus clock input of device (open drain); must be connected
to a pull-up resistor; 5 V tolerant
I2C_SDA
44 I/O I2C-bus data input/output of device (open drain); must be
connected to a pull-up resistor; 5 V tolerant
VDDC(1V8)
VSSA(PLL_1V8)
VSSD
VDDD(3V3)
VPC[7]
45
46
47
48
49
P
G
G
P
I
supply voltage for digital core (1.8 V)
analog ground reference for PLL
ground for input ports
supply voltage for input ports (3.3 V)
video port C input bit 7
VPC[6]
50 I
video port C input bit 6
VPC[5]
51 I
video port C input bit 5
VPC[4]
52 I
video port C input bit 4
VPC[3]
53 I
video port C input bit 3
VPC[2]
54 I
video port C input bit 2
VPC[1]
55 I
video port C input bit 1
VPC[0]
56 I
video port C input bit 0
VPB[7]
57 I
video port B input bit 7
VPB[6]
58 I
video port B input bit 6
VDDC(1V8)
VSSC
VPB[5]
59 P
60 G
61 I
supply voltage for digital core (1.8 V)
ground for digital core
video port B input bit 5
VPB[4]
62 I
video port B input bit 4
VPB[3]
63 I
video port B input bit 3
VPB[2]
64 I
video port B input bit 2
VPB[1]
65 I
video port B input bit 1
VCLK
66 I
video pixel clock input
VPB[0]
67 I
video port B input bit 0
VPA[7]
68 I
video port A input bit 7
VPA[6]
69 I
video port A input bit 6
VPA[5]
70 I
video port A input bit 5
VDDD(3V3)
VSSD
VSSC
VDDC(1V8)
VPA[4]
71 P
72 G
73 G
74 P
75 I
supply voltage for input ports (3.3 V)
ground for input ports
ground for digital core
supply voltage for digital core (1.8 V)
video port A input bit 4
VPA[3]
76 I
video port A input bit 3
VPA[2]
77 I
video port A input bit 2
VPA[1]
78 I
video port A input bit 1
VPA[0]
79 I
video port A input bit 0
DE/FREF
80 I
video data enable input or field reference input
[1] P = power supply; G = ground; I = input; O = output.
Rev. 01 — 19 May 2008
© NXP B.V. 2008. All rights reserved.
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