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PDF TDA9983B Data sheet ( Hoja de datos )
| Número de pieza | TDA9983B | |
| Descripción | HDMI Transmitter Up To 150 MHz Pixel Rate | |
| Fabricantes | NXP Semiconductors | |
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TDA9983B
HDMI transmitter up to 150 MHz pixel rate with 3 × 8-bit video
inputs and 4 × I2S-bus with S/PDIF
Rev. 01 — 20 May 2008
Product data sheet
1. General description
The TDA9983B is an HDMI transmitter (which also supports DVI) that enables a 3 × 8-bit
RGB or YCBCR video stream (with a pixel rate up to 150 MHz for the TDA9983BHW/15
version), up to 4 I2S-bus audio streams (with an audio sampling rate up to 192 kHz) and
the additional information required by all the HDMI 1.2a standards.
A programmable upscaling block enables a 720p/1080i output from a standard definition
input. An intrafield deinterlacer is included in the scaler.
In order to be compatible with most applications, the TDA9983B integrates a full
programmable input formatter and color space conversion block. The video input formats
accepted are YCBCR 4 : 4 : 4 (up to 3 × 8-bit), YCBCR 4 : 2 : 2 semi-planar (up to
2 × 12-bit), YCBCR 4 : 2 : 2 compliant with ITU656 and ITU656-like (up to 1 × 12-bit).
For ITU656-like formats, double edges are supported so that data can be sampled on
rising and falling edges.
The device can be controlled via an I2C-bus interface.
2. Features
I 3 × 8-bit video data input bus, CMOS and LV-TTL compatible
I Horizontal synchronization, vertical synchronization and Data Enable (DE) inputs or
VREF, HREF and FREF could be used for input data synchronization
I Pixel rate clock input can be made active on one or both edges (selectable by I2C-bus)
I The TDA9983B has 4 I2S-bus audio input channels and 1 S/PDIF channel; audio
sampling rate up to 192 kHz
I 250 MHz to 1.50 GHz HDMI transmitter operation
I Programmable input formatter and upsampler/interpolator allows input of any of the
4 : 4 : 4, 4 : 2 : 2 semi-planar, 4 : 2 : 2 ITU656 and ITU656-like formats
I Programmable color space converter:
N RGB to YCBCR
N YCBCR to RGB
I The upscaler enables a 720p/1080i output from a standard definition input using
intelligent edge interpolation
I Controllable via I2C-bus
I Low power dissipation
I 1.8 V and 3.3 V power supplies
I Power-down mode
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7. Pinning information
7.1 Pinning
TDA9983B
150 MHz pixel rate HDMI transmitter
HSYNC/HREF 1
VSYNC/VREF 2
VPP 3
AP7 4
AP6 5
AP5 6
AP4 7
AP3 8
AP2 9
AP1 10
AP0 11
ACLK 12
VDDD(3V3) 13
VSSD 14
VSSC 15
VDDC(1V8) 16
INT 17
HPD 18
DDC_SDA 19
DDC_SCL 20
TDA9983B
60 VSSC
59 VDDC(1V8)
58 VPB[6]
57 VPB[7]
56 VPC[0]
55 VPC[1]
54 VPC[2]
53 VPC[3]
52 VPC[4]
51 VPC[5]
50 VPC[6]
49 VPC[7]
48 VDDD(3V3)
47 VSSD
46 VSSA(PLL_1V8)
45 VDDC(1V8)
44 I2C_SDA
43 I2C_SCL
42 RST_N
41 A0
001aag249
Fig 2. Pin configuration
7.2 Pin description
Table 4. Pin description
Symbol
Pin Type[1] Description
HSYNC/HREF 1
I
horizontal synchronization or reference input
VSYNC/VREF 2
I
vertical synchronization or reference input
VPP 3 P programming voltage (must be connected to the ground of
the digital core in normal operation)
AP7
4I
audio port 7 input; auxiliary (AUX)
AP6
5I
audio port 6 input; S/PDIF stream
AP5
6I
audio port 5 input; optional master clock MCLK for S/PDIF
TDA9983B_1
Product data sheet
Rev. 01 — 20 May 2008
© NXP B.V. 2008. All rights reserved.
5 of 119
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TDA9983B
150 MHz pixel rate HDMI transmitter
Table 7. YCBCR 4 : 4 : 4 mappings
YCBCR 4 : 4 : 4 (3 × 8-bit) external synchronization single edge.
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.
Video port A
Video port B
Video port C
Pin
VPA[0]
VPA[1]
VPA[2]
VPA[3]
VPA[4]
VPA[5]
VPA[6]
VPA[7]
YCBCR 4 : 4 : 4
CB[0]
CB[1]
CB[2]
CB[3]
CB[4]
CB[5]
CB[6]
CB[7]
Pin
VPB[0]
VPB[1]
VPB[2]
VPB[3]
VPB[4]
VPB[5]
VPB[6]
VPB[7]
YCBCR 4 : 4 : 4
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
Pin
VPC[0]
VPC[1]
VPC[2]
VPC[3]
VPC[4]
VPC[5]
VPC[6]
VPC[7]
YCBCR 4 : 4 : 4
CR[0]
CR[1]
CR[2]
CR[3]
CR[4]
CR[5]
CR[6]
CR[7]
Control
Pin
HSYNC/HREF
VSYNC/VREF
DE/FREF
YCBCR 4 : 4 : 4
used
used
used
VCLK
HSYNC/HREF
CONTROL
INPUTS
VSYNC/VREF
DE/FREF
VPA[7:0]
CB0
CB1
CB2
CB3
VPB[7:0]
Y0
Y1
Y2
Y3
VPC[7:0]
CR0
CR1
CR2
CR3
DE could also be generated from HSYNC/HREF and VSYNC/VREF
Fig 4. Pixel encoding in YCBCR 4 : 4 : 4 (rising edge) input
...
CBxxx
CBxxx
...
Yxxx
Yxxx
...
CRxxx
CRxxx
001aag381
TDA9983B_1
Product data sheet
Rev. 01 — 20 May 2008
© NXP B.V. 2008. All rights reserved.
11 of 119
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